Inventor · disambiguated record
Shao-Fu Sanford Chu
Also filed as: CHU SHAO-FU · CHU SHAO-FU S · CHU SHAO-FU SANFORD
47 granted patents·1 pending application·1,179 citations·filing 1981–2021
98Inventor score
Files withCHARTERED SEMICONDUCTOR MFG26IBM10YANGTZE MEMORY TECH CO LTD4GLOBALFOUNDRIES SG PTE LTD2CHARTERED SEMIONDUCTOR MFG LTD1
Top patents by PatentIndex Score
48 records- 0195US6297132B1Process to control the lateral doping profile of an implanted channel regionCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Oct 2, 2001·128 cites·18 claims
- 0292US6709918B1Method for making a metal-insulator-metal (MIM) capacitor and metal resistor for a copper back-end-of-line (BEOL) technologyCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Mar 23, 2004·87 cites·30 claims
- 0391US10847534B2Staircase structures for three-dimensional memory device double-sided routingYANGTZE MEMORY TECH CO LTD·Filed 2018·Granted Nov 24, 2020·7 cites·20 claims
- 0491US5015594AProcess of making BiCMOS devices having closely spaced device regionsIBM·Filed 1988·Granted May 14, 1991·122 cites·14 claims
- 0589US9466661B2Method of fabricating a MIM capacitor with minimal voltage coefficient and a decoupling MIM capacitor and analog/RF MIM capacitor on the same chip with high-K dielectricsGLOBALFOUNDRIES INC·Filed 2014·Granted Oct 11, 2016·10 cites·10 claims
- 0687US6841847B23-D spiral stacked inductor on semiconductor materialCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Jan 11, 2005·41 cites·14 claims
- 0786US6133079AMethod for reducing substrate capacitive coupling of a thin film inductor by reverse P/N junctionsCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted Oct 17, 2000·88 cites·21 claims
- 0886US6124194AMethod of fabrication of anti-fuse integrated with dual damascene processCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted Sep 26, 2000·90 cites·13 claims
- 0985US7078998B2Via/line inductor on semiconductor materialCHARTERED SEMICONDUCTOR MFG·Filed 2004·Granted Jul 18, 2006·32 cites·11 claims
- 1085US4385975AMethod of forming wide, deep dielectric filled isolation trenches in the surface of a silicon semiconductor substrateIBM·Filed 1981·Granted May 31, 1983·60 cites·17 claims
- 1183US6117747AIntegration of MOM capacitor into dual damascene processCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted Sep 12, 2000·73 cites·20 claims
- 1281US11069596B2Through silicon contact structure and method of forming the sameYANGTZE MEMORY TECH CO LTD·Filed 2019·Granted Jul 20, 2021·2 cites·14 claims
- 1381US6284590B1Method to eliminate top metal corner shaping during bottom metal patterning for MIM capacitorsCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Sep 4, 2001·29 cites·27 claims
- 1478US6156602ASelf-aligned precise high sheet RHO register for mixed-signal applicationCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted Dec 5, 2000·43 cites·24 claims
- 1576US6372652B1Method for forming a thin-film, electrically blowable fuse with a reproducible blowing wattageCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Apr 16, 2002·33 cites·16 claims
- 1674US7951680B2Integrated circuit system employing an elevated drainGLOBALFOUNDRIES SG PTE LTD·Filed 2008·Granted May 31, 2011·5 cites·20 claims
- 1774US6291307B1Method and structure to make planar analog capacitor on the top of a STI structureCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted Sep 18, 2001·36 cites·19 claims
- 1873US5874764AModular MOSFETS for high aspect ratio applicationsIBM·Filed 1996·Granted Feb 23, 1999·30 cites·6 claims
- 1971US8115276B2Integrated circuit system employing back end of line via techniquesZHANG SHAOQING·Filed 2008·Granted Feb 14, 2012·7 cites·20 claims
- 2071US8021954B2Integrated circuit system with hierarchical capacitor and method of manufacture thereofGLOBALFOUNDRIES SG PTE LTD·Filed 2009·Granted Sep 20, 2011·5 cites·25 claims
- 2171US7022578B2Heterojunction bipolar transistor using reverse emitter windowCHARTERED SEMICONDUCTOR MFG·Filed 2003·Granted Apr 4, 2006·18 cites·10 claims
- 2270US11721609B2Through silicon contact structure and method of forming the sameYANGTZE MEMORY TECH CO LTD·Filed 2021·Granted Aug 8, 2023·0 cites·20 claims
- 2370US11710679B2Through silicon contact structure and method of forming the sameYANGTZE MEMORY TECH CO LTD·Filed 2021·Granted Jul 25, 2023·0 cites·20 claims
- 2470US6284594B1Formation of an interpoly capacitor structure using a chemical mechanical polishing procedureCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Sep 4, 2001·16 cites·24 claims
- 2570US5484738AMethod of forming silicon on oxide semiconductor device structure for BiCMOS integrated circuitsIBM·Filed 1995·Granted Jan 16, 1996·34 cites·4 claims
- 2666US8536016B2Integrated circuit system with hierarchical capacitor and method of manufacture thereofCHU SHAO-FU SANFORD·Filed 2011·Granted Sep 17, 2013·3 cites·25 claims
- 2766US6410394B1Method for forming self-aligned channel implants using a gate poly reverse maskCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted Jun 25, 2002·21 cites·8 claims
- 2864US7268412B2Double polysilicon bipolar transistorCHARTERED SEMICONDUCTOR MFG·Filed 2005·Granted Sep 11, 2007·2 cites·10 claims
- 2960US6489191B2Method for forming self-aligned channel implants using a gate poly reverse maskCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Dec 3, 2002·8 cites·10 claims
- 3060US5331199ABipolar transistor with reduced topographyIBM·Filed 1993·Granted Jul 19, 1994·28 cites·5 claims
- 3159US5521399AAdvanced silicon on oxide semiconductor device structure for BiCMOS integrated circuitIBM·Filed 1994·Granted May 28, 1996·24 cites·16 claims
- 3258US6881976B1Heterojunction BiCMOS semiconductorCHARTERED SEMICONDUCTOR MFG·Filed 2003·Granted Apr 19, 2005·7 cites·20 claims
- 3357US6972237B2Lateral heterojunction bipolar transistor and method of manufacture using selective epitaxial growthCHARTERED SEMICONDUCTOR MFG·Filed 2003·Granted Dec 6, 2005·7 cites·32 claims
- 3456US7721414B2Method of manufacturing 3-D spiral stacked inductor on semiconductor materialCHARTERED SEMICONDUCTOR MFG·Filed 2004·Granted May 25, 2010·6 cites·10 claims
- 3556US6750750B2Via/line inductor on semiconductor materialCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Jun 15, 2004·6 cites·10 claims
- 3652US5266505AImage reversal process for self-aligned implants in planar epitaxial-base bipolar transistorsIBM·Filed 1992·Granted Nov 30, 1993·15 cites·2 claims
- 3749US7049201B2Method and apparatus for a heterojunction bipolar transistor using self-aligned epitaxyCHARTERED SEMIONDUCTOR MFG LTD·Filed 2003·Granted May 23, 2006·6 cites·18 claims
- 3849US6936519B2Double polysilicon bipolar transistor and method of manufacture thereforCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Aug 30, 2005·3 cites·5 claims
- 3947US7238971B2Self-aligned lateral heterojunction bipolar transistorCHARTERED SEMICONDUCTOR MFG·Filed 2005·Granted Jul 3, 2007·0 cites·10 claims
- 4047US5721144AMethod of making trimmable modular MOSFETs for high aspect ratio applicationsIBM·Filed 1995·Granted Feb 24, 1998·9 cites·11 claims
- 4145US6924202B2Heterojunction bipolar transistor with self-aligned emitter and sidewall base contactCHARTERED SEMICONDUCTOR MFG·Filed 2003·Granted Aug 2, 2005·2 cites·20 claims
- 4244US5234846AMethod of making bipolar transistor with reduced topographyIBM·Filed 1992·Granted Aug 10, 1993·15 cites·10 claims
- 4343US6908824B2Self-aligned lateral heterojunction bipolar transistorCHARTERED SEMICONDUCTOR MFG·Filed 2003·Granted Jun 21, 2005·1 cites·10 claims
- 4443US5229322AMethod of making low resistance substrate or buried layer contactIBM·Filed 1991·Granted Jul 20, 1993·13 cites·12 claims
- 4540US8138051B2Integrated circuit system with high voltage transistor and method of manufacture thereofDONG YEMIN·Filed 2009·Granted Mar 20, 2012·0 cites·20 claims
- 4637US9269770B2Integrated circuit system with double doped drain transistorLI YISUO·Filed 2007·Granted Feb 23, 2016·0 cites·20 claims
- 4737US6159759AMethod to form liquid crystal displays using a triple damascene techniqueCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted Dec 12, 2000·7 cites·20 claims
- 4836US2005145953A1Heterojunction BiCMOS integrated circuits and method thereforCHARTERED SEMICONDUCTOR MFG·Filed 2004·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →