Inventor · disambiguated record
Michael Ju Hyeok Lee
Also filed as: LEE MICHAEL · LEE MICHAEL E · LEE MICHAEL J · LEE MICHAEL J H
45 granted patents·5 pending applications·396 citations·filing 1996–2021
98Inventor score
Top patents by PatentIndex Score
50 records- 0196US6433589B1Sense amplifier and method for sensing signals in a silicon-on-insulator integrated circuitIBM·Filed 2001·Granted Aug 13, 2002·84 cites·14 claims
- 0279US8014215B2Cache array power savings through a design structure for valid bit detectionIBM·Filed 2009·Granted Sep 6, 2011·9 cites·24 claims
- 0379US5852373AStatic-dynamic logic circuitIBM·Filed 1996·Granted Dec 22, 1998·38 cites·5 claims
- 0475US7283404B2Content addressable memory including a dual mode cycle boundary latchIBM·Filed 2005·Granted Oct 16, 2007·11 cites·6 claims
- 0574US6826090B1Apparatus and method for a radiation resistant latchIBM·Filed 2003·Granted Nov 30, 2004·21 cites·20 claims
- 0673US7506230B2Transient noise detection scheme and apparatusIBM·Filed 2005·Granted Mar 17, 2009·6 cites·10 claims
- 0773US7167385B2Method and apparatus for controlling the timing of precharge in a content addressable memory systemIBM·Filed 2005·Granted Jan 23, 2007·9 cites·20 claims
- 0872US7936638B2Enhanced programmable pulsewidth modulating circuit for array clock generationIBM·Filed 2009·Granted May 3, 2011·6 cites·19 claims
- 0972US7202704B2Leakage sensing and keeper circuit for proper operation of a dynamic circuitIBM·Filed 2004·Granted Apr 10, 2007·14 cites·20 claims
- 1072US6825691B1Apparatus and method for a radiation resistant latch with integrated scanIBM·Filed 2003·Granted Nov 30, 2004·19 cites·20 claims
- 1170US7936198B2Progamable control clock circuit for arraysIBM·Filed 2008·Granted May 3, 2011·4 cites·16 claims
- 1268US7116569B2Method and apparatus for selecting operating characteristics of a content addressable memory by using a compare maskIBM·Filed 2005·Granted Oct 3, 2006·7 cites·20 claims
- 1367US7788444B2Multi-hit detection in associative memoriesIBM·Filed 2006·Granted Aug 31, 2010·6 cites·20 claims
- 1467US7552413B2System and computer program for verifying performance of an array by simulating operation of edge cells in a full array modelIBM·Filed 2008·Granted Jun 23, 2009·3 cites·13 claims
- 1564US6002271ADynamic MOS logic circuit without charge sharing noiseIBM·Filed 1997·Granted Dec 14, 1999·19 cites·14 claims
- 1663US7468929B2Apparatus for SRAM array power reduction through majority evaluationIBM·Filed 2006·Granted Dec 23, 2008·5 cites·12 claims
- 1762US6052008AGeneration of true and complement signals in dynamic circuitsIBM·Filed 1997·Granted Apr 18, 2000·21 cites·13 claims
- 1862US6046606ASoft error protected dynamic circuitIBM·Filed 1998·Granted Apr 4, 2000·40 cites·17 claims
- 1960US6107852AMethod and device for the reduction of latch insertion delayIBM·Filed 1998·Granted Aug 22, 2000·16 cites·11 claims
- 2059US7424691B2Method for verifying performance of an array by simulating operation of edge cells in a full array modelIBM·Filed 2006·Granted Sep 9, 2008·1 cites·7 claims
- 2159US6960941B2Latch circuit capable of ensuring race-free staging for signals in dynamic logic circuitsIBM·Filed 2004·Granted Nov 1, 2005·8 cites·9 claims
- 2258US6934181B2Reducing sub-threshold leakage in a memory arrayIBM·Filed 2003·Granted Aug 23, 2005·9 cites·16 claims
- 2356US9042149B2Volatile memory access via shared bitlinesIBM·Filed 2013·Granted May 26, 2015·1 cites·20 claims
- 2455US7813189B2Array data input latch and data clocking schemeIBM·Filed 2008·Granted Oct 12, 2010·3 cites·20 claims
- 2555US6914450B2Register-file bit-read method and apparatusIBM·Filed 2003·Granted Jul 5, 2005·8 cites·20 claims
- 2652US11908519B2Pre-compare operation for compact low-leakage dual-compare cam cellIBM·Filed 2021·Granted Feb 20, 2024·0 cites·20 claims
- 2752US8237481B2Low power programmable clock delay generator with integrated decode functionCHAN YUEN H·Filed 2008·Granted Aug 7, 2012·2 cites·5 claims
- 2852US7092270B2Apparatus and method for detecting multiple hits in CAM arraysIBM·Filed 2004·Granted Aug 15, 2006·8 cites·20 claims
- 2950US7304352B2Alignment insensitive D-cache cellIBM·Filed 2005·Granted Dec 4, 2007·3 cites·14 claims
- 3049US11837289B2Compact low-leakage multi-bit compare CAM cellIBM·Filed 2021·Granted Dec 5, 2023·0 cites·20 claims
- 3149US6341095B1Apparatus for increasing pulldown rate of a bitline in a memory device during a read operationIBM·Filed 2001·Granted Jan 22, 2002·6 cites·20 claims
- 3248US7613944B2Programmable local clock buffer capable of varying initial settingsIBM·Filed 2006·Granted Nov 3, 2009·0 cites·21 claims
- 3348US7012839B1Register file apparatus and method incorporating read-after-write blocking using detection cellsIBM·Filed 2004·Granted Mar 14, 2006·4 cites·15 claims
- 3444US7099201B1Multifunctional latch circuit for use with both SRAM array and self test deviceIBM·Filed 2005·Granted Aug 29, 2006·1 cites·20 claims
- 3544US7002860B2Multilevel register-file bit-read method and apparatusIBM·Filed 2003·Granted Feb 21, 2006·4 cites·9 claims
- 3644US2014098597A1Single-ended volatile memory accessIBM·Filed 2013·Application pending·0 cites
- 3744US2007125849A1Checkout systemIBM·Filed 2005·Application pending·0 cites
- 3842US7561489B2System and method of selective row energization based on write dataIBM·Filed 2008·Granted Jul 14, 2009·0 cites·15 claims
- 3941US2013141992A1Volatile memory access via shared bitlinesLEE MICHAEL JU HYEOK·Filed 2011·Application pending·0 cites
- 4041US2013141997A1Single-ended volatile memory accessLEE MICHAEL JU HYEOK·Filed 2011·Application pending·0 cites
- 4140US7379348B2System and method of selective row energization based on write dataIBM·Filed 2006·Granted May 27, 2008·0 cites·2 claims
- 4240US7142463B2Register file method incorporating read-after-write blocking using detection cellsIBM·Filed 2005·Granted Nov 28, 2006·0 cites·7 claims
- 4339US9704568B1Reducing SRAM power using strategic data pattern storageIBM·Filed 2016·Granted Jul 11, 2017·0 cites·20 claims
- 4438US7804728B2Information handling system with SRAM precharge power conservationIBM·Filed 2008·Granted Sep 28, 2010·0 cites·14 claims
- 4537US2007229132A1Scannable domino latch redundancy for soft error rate protection with collision avoidanceCHU SAM G·Filed 2006·Application pending·0 cites
- 4636US7788443B2Transparent multi-hit correction in associative memoriesIBM·Filed 2006·Granted Aug 31, 2010·0 cites·18 claims
- 4735US7015723B2Dynamic-static logical control element for signaling an interval between the end of a control signal and a logical evaluationIBM·Filed 2004·Granted Mar 21, 2006·0 cites·20 claims
- 4830US8375172B2Preventing fast read before write in static random access memory arraysIBM·Filed 2010·Granted Feb 12, 2013·0 cites·21 claims
- 4930US7466647B2Efficient muxing scheme to allow for bypass and array accessIBM·Filed 2005·Granted Dec 16, 2008·0 cites·3 claims
- 5030US6037804AReduced power dynamic logic circuit that inhibits reevaluation of stable inputsIBM·Filed 1998·Granted Mar 14, 2000·0 cites·21 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →