Inventor · disambiguated record
Vignyan Reddy Kothinti Naresh
Also filed as: KOTHINTI NARESH VIGNYAN REDDY
21 granted patents·5 pending applications·31 citations·filing 2015–2022
91Inventor score
Top patents by PatentIndex Score
26 records- 0195US11061677B1Recovering register mapping state of a flushed instruction employing a snapshot of another register mapping state and traversing reorder buffer (ROB) entries in a processorMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2020·Granted Jul 13, 2021·9 cites·40 claims
- 0291US11494191B1Tracking exact convergence to guide the recovery process in response to a mispredicted branchMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2021·Granted Nov 8, 2022·2 cites·20 claims
- 0389US9830152B2Selective storing of previously decoded instructions of frequently-called instruction sequences in an instruction sequence buffer to be executed by a processorQUALCOMM INC·Filed 2015·Granted Nov 28, 2017·8 cites·30 claims
- 0481US11269642B2Dynamic hammock branch training for branch hammock detection in an instruction stream executing in a processorMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2019·Granted Mar 8, 2022·3 cites·19 claims
- 0581US10877768B1Minimizing traversal of a processor reorder buffer (ROB) for register rename map table (RMT) state recovery for interrupted instruction recovery in a processorMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2019·Granted Dec 29, 2020·3 cites·26 claims
- 0678US10929139B2Providing predictive instruction dispatch throttling to prevent resource overflows in out-of-order processor (OOP)-based devicesQUALCOMM INC·Filed 2018·Granted Feb 23, 2021·2 cites·21 claims
- 0775US11327763B2Opportunistic consumer instruction steering based on producer instruction value prediction in a multi-cluster processorMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2020·Granted May 10, 2022·1 cites·22 claims
- 0875US10255074B2Selective flushing of instructions in an instruction pipeline in a processor back to an execution-resolved target address, in response to a precise interruptQUALCOMM INC·Filed 2015·Granted Apr 9, 2019·2 cites·30 claims
- 0970US11061683B2Limiting replay of load-based control independent (CI) instructions in speculative misprediction recovery in a processorMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2019·Granted Jul 13, 2021·1 cites·29 claims
- 1069US11755330B2Tracking exact convergence to guide the recovery process in response to a mispredicted branchMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2022·Granted Sep 12, 2023·0 cites·20 claims
- 1153US11036512B2Systems and methods for processing instructions having wide immediate operandsMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2019·Granted Jun 15, 2021·0 cites·20 claims
- 1252US10783011B2Deadlock free resource management in block based computing architecturesQUALCOMM INC·Filed 2017·Granted Sep 22, 2020·0 cites·13 claims
- 1351US11068272B2Tracking and communication of direct/indirect source dependencies of producer instructions executed in a processor to source dependent consumer instructions to facilitate processor optimizationsMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2019·Granted Jul 20, 2021·0 cites·20 claims
- 1451US10896041B1Enabling early execution of move-immediate instructions having variable immediate value sizes in processor-based devicesMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2019·Granted Jan 19, 2021·0 cites·20 claims
- 1548US11061824B2Deferring cache state updates in a non-speculative cache memory in a processor-based system in response to a speculative data request until the speculative data request becomes non-speculativeMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2019·Granted Jul 13, 2021·0 cites·35 claims
- 1644US11698789B2Restoring speculative history used for making speculative predictions for instructions processed in a processor employing control independence techniquesMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2020·Granted Jul 11, 2023·0 cites·26 claims
- 1743US11392387B2Predicting load-based control independent (CI) register data independent (DI) (CIRDI) instructions as CI memory data dependent (DD) (CIMDD) instructions for replay in speculative misprediction recovery in a processorMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2020·Granted Jul 19, 2022·0 cites·24 claims
- 1843US11392410B2Operand pool instruction reservation clustering in a scheduler circuit in a processorMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2020·Granted Jul 19, 2022·0 cites·24 claims
- 1943US10725782B2Providing variable interpretation of usefulness indicators for memory tables in processor-based systemsQUALCOMM INC·Filed 2017·Granted Jul 28, 2020·0 cites·20 claims
- 2043US10437592B2Reduced logic level operation folding of context history in a history register in a prediction system for a processor-based systemQUALCOMM INC·Filed 2017·Granted Oct 8, 2019·0 cites·45 claims
- 2141US11620133B2Reduction of data cache access in a processing systemQUALCOMM INC·Filed 2019·Granted Apr 4, 2023·0 cites·17 claims
- 2241US2019087184A1Select in-order instruction pick using an out of order instruction pickerQUALCOMM INC·Filed 2017·Application pending·0 cites
- 2339US2018081690A1Performing distributed branch prediction using fused processor cores in processor-based systemsQUALCOMM INC·Filed 2016·Application pending·0 cites
- 2439US2018081806A1Memory violation predictionQUALCOMM INC·Filed 2016·Application pending·0 cites
- 2539US2018089085A1Reusing trained prefetchersQUALCOMM INC·Filed 2016·Application pending·0 cites
- 2638US2019065060A1Caching instruction block header data in block architecture processor-based systemsQUALCOMM INC·Filed 2017·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →