Inventor · disambiguated record
Yusuf Cagatay Tekmen
Also filed as: TEKMEN YUSUF CAGATAY
16 granted patents·7 pending applications·29 citations·filing 2012–2024
88Inventor score
Technology areasG06F
Top patents by PatentIndex Score
23 records- 0195US11061677B1Recovering register mapping state of a flushed instruction employing a snapshot of another register mapping state and traversing reorder buffer (ROB) entries in a processorMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2020·Granted Jul 13, 2021·9 cites·40 claims
- 0285US11113068B1Performing flush recovery using parallel walks of sliced reorder buffers (SROBs)MICROSOFT TECHNOLOGY LICENSING LLC·Filed 2020·Granted Sep 7, 2021·2 cites·20 claims
- 0385US9164772B2Hybrid queue for storing instructions from fetch queue directly in out-of-order queue or temporarily in in-order queue until space is availableDOCKSER KENNETH ALAN·Filed 2012·Granted Oct 20, 2015·10 cites·23 claims
- 0481US10877768B1Minimizing traversal of a processor reorder buffer (ROB) for register rename map table (RMT) state recovery for interrupted instruction recovery in a processorMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2019·Granted Dec 29, 2020·3 cites·26 claims
- 0575US11327763B2Opportunistic consumer instruction steering based on producer instruction value prediction in a multi-cluster processorMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2020·Granted May 10, 2022·1 cites·22 claims
- 0671US9304774B2Processor with a coprocessor having early access to not-yet issued instructionsDOCKSER KENNETH ALAN·Filed 2012·Granted Apr 5, 2016·3 cites·24 claims
- 0770US10956162B2Operand-based reach explicit dataflow processors, and related methods and computer-readable mediaMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2019·Granted Mar 23, 2021·1 cites·30 claims
- 0862US12511127B2Dynamic reconfiguration of a multi-core processor to a unified coreNVIDIA CORP·Filed 2024·Granted Dec 30, 2025·0 cites·21 claims
- 0951US10896041B1Enabling early execution of move-immediate instructions having variable immediate value sizes in processor-based devicesMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2019·Granted Jan 19, 2021·0 cites·20 claims
- 1051US2025265224A1Dynamic reconfiguration of a unified core processor to a multi-core processorNVIDIA CORP·Filed 2024·Application pending·0 cites
- 1149US11669333B2Method, apparatus, and system for reducing live readiness calculations in reservation stationsQUALCOMM INC·Filed 2018·Granted Jun 6, 2023·0 cites·15 claims
- 1247US10860328B2Providing late physical register allocation and early physical register release in out-of-order processor (OOP)-based devices implementing a checkpoint-based architectureQUALCOMM INC·Filed 2018·Granted Dec 8, 2020·0 cites·42 claims
- 1346US11023243B2Latency-based instruction reservation station clustering in a scheduler circuit in a processorMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2019·Granted Jun 1, 2021·0 cites·22 claims
- 1445US2022398100A1Processors employing memory data bypassing in memory data dependent instructions as a store data forwarding mechanism, and related methodsMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2021·Application pending·0 cites
- 1543US11392410B2Operand pool instruction reservation clustering in a scheduler circuit in a processorMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2020·Granted Jul 19, 2022·0 cites·24 claims
- 1643US10514921B2Fast reuse of physical register namesQUALCOMM INC·Filed 2017·Granted Dec 24, 2019·0 cites·12 claims
- 1742US11593117B2Combining load or store instructionsQUALCOMM INC·Filed 2018·Granted Feb 28, 2023·0 cites·40 claims
- 1841US11803389B2Reach matrix scheduler circuit for scheduling instructions to be executed in a processorMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2020·Granted Oct 31, 2023·0 cites·9 claims
- 1941US2013173886A1Processor with Hazard Tracking Employing Register Range ComparesDOCKSER KENNETH ALAN·Filed 2012·Application pending·0 cites
- 2041US2012204008A1Processor with a Hybrid Instruction Queue with Instruction Elaboration Between SectionsDOCKSER KENNETH ALAN·Filed 2012·Application pending·0 cites
- 2139US2019294443A1Providing early pipeline optimization of conditional instructions in processor-based systemsQUALCOMM INC·Filed 2018·Application pending·0 cites
- 2236US2017046160A1Efficient handling of register filesQUALCOMM INC·Filed 2016·Application pending·0 cites
- 2332US2017046164A1High performance recovery from misspeculation of load latencyQUALCOMM INC·Filed 2015·Application pending·0 cites
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →