Inventor · disambiguated record
Shivam Priyadarshi
Also filed as: PRIYADARSHI SHIVAM
29 granted patents·10 pending applications·81 citations·filing 2015–2022
94Inventor score
Top patents by PatentIndex Score
39 records- 0196US10108417B2Storing narrow produced values for instruction operands directly in a register map in an out-of-order processorQUALCOMM INC·Filed 2015·Granted Oct 23, 2018·42 cites·30 claims
- 0295US11061677B1Recovering register mapping state of a flushed instruction employing a snapshot of another register mapping state and traversing reorder buffer (ROB) entries in a processorMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2020·Granted Jul 13, 2021·9 cites·40 claims
- 0391US11494191B1Tracking exact convergence to guide the recovery process in response to a mispredicted branchMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2021·Granted Nov 8, 2022·2 cites·20 claims
- 0489US9830152B2Selective storing of previously decoded instructions of frequently-called instruction sequences in an instruction sequence buffer to be executed by a processorQUALCOMM INC·Filed 2015·Granted Nov 28, 2017·8 cites·30 claims
- 0587US10223278B2Selective bypassing of allocation in a cacheQUALCOMM INC·Filed 2016·Granted Mar 5, 2019·6 cites·28 claims
- 0685US11113068B1Performing flush recovery using parallel walks of sliced reorder buffers (SROBs)MICROSOFT TECHNOLOGY LICENSING LLC·Filed 2020·Granted Sep 7, 2021·2 cites·20 claims
- 0781US10877768B1Minimizing traversal of a processor reorder buffer (ROB) for register rename map table (RMT) state recovery for interrupted instruction recovery in a processorMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2019·Granted Dec 29, 2020·3 cites·26 claims
- 0881US10831254B2Allocating power between multiple central processing units (CPUs) in a multi-CPU processor based on total current availability and individual CPU quality-of-service (QoS) requirementsQUALCOMM INC·Filed 2018·Granted Nov 10, 2020·4 cites·26 claims
- 0975US11327763B2Opportunistic consumer instruction steering based on producer instruction value prediction in a multi-cluster processorMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2020·Granted May 10, 2022·1 cites·22 claims
- 1070US11061683B2Limiting replay of load-based control independent (CI) instructions in speculative misprediction recovery in a processorMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2019·Granted Jul 13, 2021·1 cites·29 claims
- 1169US11755330B2Tracking exact convergence to guide the recovery process in response to a mispredicted branchMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2022·Granted Sep 12, 2023·0 cites·20 claims
- 1268US9851774B2Method and apparatus for dynamic clock and voltage scaling in a computer processor based on program phaseQUALCOMM INC·Filed 2016·Granted Dec 26, 2017·1 cites·29 claims
- 1367US10474462B2Dynamic pipeline throttling using confidence-based weighting of in-flight branch instructionsQUALCOMM INC·Filed 2016·Granted Nov 12, 2019·1 cites·30 claims
- 1465US10169240B2Reducing memory access bandwidth based on prediction of memory request sizeQUALCOMM INC·Filed 2016·Granted Jan 1, 2019·1 cites·13 claims
- 1557US10551896B2Method and apparatus for dynamic clock and voltage scaling in a computer processor based on program phaseQUALCOMM INC·Filed 2017·Granted Feb 4, 2020·0 cites·36 claims
- 1656US10185668B2Cost-aware cache replacementQUALCOMM INC·Filed 2016·Granted Jan 22, 2019·0 cites·19 claims
- 1755US2019018798A1Cost-aware cache replacementQUALCOMM INC·Filed 2018·Application pending·0 cites
- 1853US11036512B2Systems and methods for processing instructions having wide immediate operandsMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2019·Granted Jun 15, 2021·0 cites·20 claims
- 1951US10896041B1Enabling early execution of move-immediate instructions having variable immediate value sizes in processor-based devicesMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2019·Granted Jan 19, 2021·0 cites·20 claims
- 2049US11669333B2Method, apparatus, and system for reducing live readiness calculations in reservation stationsQUALCOMM INC·Filed 2018·Granted Jun 6, 2023·0 cites·15 claims
- 2148US11061824B2Deferring cache state updates in a non-speculative cache memory in a processor-based system in response to a speculative data request until the speculative data request becomes non-speculativeMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2019·Granted Jul 13, 2021·0 cites·35 claims
- 2247US10860328B2Providing late physical register allocation and early physical register release in out-of-order processor (OOP)-based devices implementing a checkpoint-based architectureQUALCOMM INC·Filed 2018·Granted Dec 8, 2020·0 cites·42 claims
- 2346US11023243B2Latency-based instruction reservation station clustering in a scheduler circuit in a processorMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2019·Granted Jun 1, 2021·0 cites·22 claims
- 2445US2022398100A1Processors employing memory data bypassing in memory data dependent instructions as a store data forwarding mechanism, and related methodsMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2021·Application pending·0 cites
- 2544US11698789B2Restoring speculative history used for making speculative predictions for instructions processed in a processor employing control independence techniquesMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2020·Granted Jul 11, 2023·0 cites·26 claims
- 2644US10379863B2Slice construction for pre-executing data dependent loadsQUALCOMM INC·Filed 2017·Granted Aug 13, 2019·0 cites·27 claims
- 2743US11392387B2Predicting load-based control independent (CI) register data independent (DI) (CIRDI) instructions as CI memory data dependent (DD) (CIMDD) instructions for replay in speculative misprediction recovery in a processorMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2020·Granted Jul 19, 2022·0 cites·24 claims
- 2843US11392410B2Operand pool instruction reservation clustering in a scheduler circuit in a processorMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2020·Granted Jul 19, 2022·0 cites·24 claims
- 2943US10303608B2Intelligent data prefetching using address delta predictionQUALCOMM INC·Filed 2017·Granted May 28, 2019·0 cites·20 claims
- 3043US2019370176A1Adaptively predicting usefulness of prefetches generated by hardware prefetch engines in processor-based devicesQUALCOMM INC·Filed 2018·Application pending·0 cites
- 3142US2019013062A1Selective refresh mechanism for dramQUALCOMM INC·Filed 2017·Application pending·0 cites
- 3241US10223118B2Providing references to previously decoded instructions of recently-provided instructions to be executed by a processorQUALCOMM INC·Filed 2016·Granted Mar 5, 2019·0 cites·30 claims
- 3341US2019034354A1Filtering insertion of evicted cache entries predicted as dead-on-arrival (doa) into a last level cache (llc) memory of a cache memory systemQUALCOMM INC·Filed 2017·Application pending·0 cites
- 3440US10635446B2Reconfiguring execution pipelines of out-of-order (OOO) computer processors based on phase training and predictionQUALCOMM INC·Filed 2015·Granted Apr 28, 2020·0 cites·33 claims
- 3539US2019065384A1Expediting cache misses through cache hit predictionQUALCOMM INC·Filed 2017·Application pending·0 cites
- 3638US2017090936A1Method and apparatus for dynamically tuning speculative optimizations based on instruction signatureQUALCOMM INC·Filed 2016·Application pending·0 cites
- 3737US2017090508A1Method and apparatus for effective clock scaling at exposed cache stallsQUALCOMM INC·Filed 2015·Application pending·0 cites
- 3836US2017046159A1Power efficient fetch adaptationQUALCOMM INC·Filed 2015·Application pending·0 cites
- 3935US2017060593A1Hierarchical register file systemQUALCOMM INC·Filed 2015·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →