Inventor · disambiguated record
Douglas M. Dewanz
Also filed as: DEWANZ DOUGLAS M · DEWANZ DOUGLAS MICHAEL
20 granted patents·133 citations·filing 1987–2014
92Inventor score
Top patents by PatentIndex Score
20 records- 0184US6643804B1Stability test for silicon on insulator SRAM memory cells utilizing bitline precharge stress operations to stress memory cells under testIBM·Filed 2000·Granted Nov 4, 2003·37 cites·31 claims
- 0280US8809156B1Method for implementing deep trench enabled high current capable bipolar transistor for current switching and output driver applicationsIBM·Filed 2013·Granted Aug 19, 2014·5 cites·13 claims
- 0378US4849904AMacro structural arrangement and method for generating macros for VLSI semiconductor circuit devicesIBM·Filed 1987·Granted Jul 18, 1989·63 cites·26 claims
- 0470US9252100B2Multiple-patterned semiconductor device channelsIBM·Filed 2013·Granted Feb 2, 2016·2 cites·11 claims
- 0570US9082624B2Signal path of a multiple-patterned semiconductor deviceIBM·Filed 2013·Granted Jul 14, 2015·2 cites·12 claims
- 0664US9111935B2Multiple-patterned semiconductor device channelsIBM·Filed 2013·Granted Aug 18, 2015·1 cites·18 claims
- 0764US9099471B2Semiconductor device channelsIBM·Filed 2013·Granted Aug 4, 2015·1 cites·20 claims
- 0864US9070751B2Semiconductor device channelsIBM·Filed 2013·Granted Jun 30, 2015·1 cites·20 claims
- 0960US6275427B1Stability test for silicon on insulator SRAM memory cells utilizing disturb operations to stress memory cells under testIBM·Filed 2000·Granted Aug 14, 2001·11 cites·30 claims
- 1057US9093451B2Signal path and method of manufacturing a multiple-patterned semiconductor deviceIBM·Filed 2013·Granted Jul 28, 2015·0 cites·6 claims
- 1157US6404686B1High performance, low cell stress, low power, SOI CMOS latch-type sensing method and apparatusIBM·Filed 2001·Granted Jun 11, 2002·9 cites·19 claims
- 1256US9099462B2Signal path and method of manufacturing a multiple-patterned semiconductor deviceIBM·Filed 2013·Granted Aug 4, 2015·0 cites·11 claims
- 1355US9087879B2Method of making semiconductor device with distinct multiple-patterned conductive tracks on a same levelIBM·Filed 2014·Granted Jul 21, 2015·0 cites·7 claims
- 1455US8866306B2Signal path and method of manufacturing a multiple-patterned semiconductor deviceIBM·Filed 2013·Granted Oct 21, 2014·0 cites·6 claims
- 1554US9099533B2Semiconductor device with distinct multiple-patterned conductive tracks on a same levelIBM·Filed 2013·Granted Aug 4, 2015·0 cites·13 claims
- 1653US9076848B2Semiconductor device channelsIBM·Filed 2013·Granted Jul 7, 2015·0 cites·20 claims
- 1752US9105639B2Semiconductor device channelsIBM·Filed 2013·Granted Aug 11, 2015·0 cites·18 claims
- 1851US9021407B2Signal path of a multiple-patterned semiconductor deviceIBM·Filed 2013·Granted Apr 28, 2015·0 cites·8 claims
- 1947US9369308B2Signal transmission reducing coupling caused delay variationIBM·Filed 2013·Granted Jun 14, 2016·0 cites·10 claims
- 2040US8107309B2Bias temperature instability-influenced storage cellDEWANZ DOUGLAS M·Filed 2009·Granted Jan 31, 2012·1 cites·12 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →