Inventor · disambiguated record
Ching-Lung Tong
Also filed as: TONG CHING L · TONG CHING LUNG · TONG CHING-LUNG L
11 granted patents·2 pending applications·52 citations·filing 2000–2024
87Inventor score
Top patents by PatentIndex Score
13 records- 0186US7382844B2Methods to self-synchronize clocks on multiple chips in a systemIBM·Filed 2005·Granted Jun 3, 2008·19 cites·3 claims
- 0282US11775004B2Phase aligning and calibrating clocks from one phase lock loop (PLL) for a two-chip die moduleIBM·Filed 2021·Granted Oct 3, 2023·1 cites·8 claims
- 0374US7568138B2Method to prevent firmware defects from disturbing logic clocks to improve system reliabilityIBM·Filed 2006·Granted Jul 28, 2009·8 cites·6 claims
- 0473US8898503B2Low latency data transfer between clock domains operated in various synchronization modesIBM·Filed 2013·Granted Nov 25, 2014·3 cites·20 claims
- 0573US8295419B2Method and apparatus for generating synchronization signals for synchronizing multiple chips in a systemHWANG CHARLIE C·Filed 2010·Granted Oct 23, 2012·4 cites·11 claims
- 0672US12111684B2Phase aligning and calibrating clocks from one phase lock loop (PLL) for a two-chip die moduleIBM·Filed 2023·Granted Oct 8, 2024·0 cites·8 claims
- 0770US7826579B2Method and apparatus for generating synchronization signals for synchronizing multiple chips in a systemIBM·Filed 2006·Granted Nov 2, 2010·4 cites·5 claims
- 0860US6333680B1Method and system for characterizing coupling capacitance between integrated circuit interconnectsIBM·Filed 2000·Granted Dec 25, 2001·10 cites·18 claims
- 0955US2025334999A1Clock synchronization in a multichip moduleIBM·Filed 2024·Application pending·0 cites
- 1051US7313747B2Measuring microprocessor susceptibility to internal noise generationIBM·Filed 2006·Granted Dec 25, 2007·1 cites·33 claims
- 1151US2025321608A1Local clock driven detune on a continuous clock gridIBM·Filed 2024·Application pending·0 cites
- 1249US7146520B2Method and apparatus for controlling clocks in a processor with mirrored unitsIBM·Filed 2003·Granted Dec 5, 2006·2 cites·9 claims
- 1339US8479070B2Integrated circuit arrangement for test inputsBAUR ULRICH·Filed 2010·Granted Jul 2, 2013·0 cites·16 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →