Inventor · disambiguated record
Shen Lin
Also filed as: LIN SHEN · LIN SHEN-TIEN
11 granted patents·3 pending applications·171 citations·filing 2000–2004
91Inventor score
Files withHEWLETT PACKARD DEVELOPMENT CO5HEWLETT PACKARD CO2IND TECH RES INST2APACHE DESIGN SOLUTIONS INC1HEWLETT PACKARD DEVELOPMENT LP1
Top patents by PatentIndex Score
14 records- 0180US7228468B2Method and apparatus of build-in self-diagnosis and repair in a memory with syndrome identificationIND TECH RES INST·Filed 2004·Granted Jun 5, 2007·28 cites·19 claims
- 0276US6981230B1On-chip power-ground inductance modeling using effective self-loop-inductanceAPACHE DESIGN SOLUTIONS INC·Filed 2002·Granted Dec 27, 2005·26 cites·24 claims
- 0375US6487703B1Method and system for screening a VLSI design for inductive coupling noiseHEWLETT PACKARD CO·Filed 2001·Granted Nov 26, 2002·29 cites·20 claims
- 0474US6434724B1Method for extracting inductance parameters from a circuit designHEWLETT PACKARD CO·Filed 2000·Granted Aug 13, 2002·28 cites·7 claims
- 0568US6621305B2Partial swing low power CMOS logic circuitsHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Sep 16, 2003·15 cites·17 claims
- 0665US6566924B2Parallel push algorithm detecting constraints to minimize clock skewHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted May 20, 2003·14 cites·21 claims
- 0763US6567960B2System for improving circuit simulations by utilizing a simplified circuit model based on effective capacitance and inductance valuesHEWLETT PACKARD DEVELOPMENT LP·Filed 2001·Granted May 20, 2003·10 cites·20 claims
- 0859US6925555B2System and method for determining a plurality of clock delay values using an optimization algorithmHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Aug 2, 2005·8 cites·23 claims
- 0955US6981231B2System and method to reduce leakage power in an electronic deviceHEWLETT PACKARD DEVELOPMENT CO·Filed 2002·Granted Dec 27, 2005·5 cites·14 claims
- 1051US6661281B2Method for reducing current surge using multi-stage ramp shuntingHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Dec 9, 2003·5 cites·26 claims
- 1146US6937106B2Built-in jitter measurement circuit for voltage controlled oscillator and phase locked loopIND TECH RES INST·Filed 2004·Granted Aug 30, 2005·3 cites·6 claims
- 1241US2003212538A1Method for full-chip vectorless dynamic IR and timing impact analysis in IC designsFiled 2003·Application pending·0 cites
- 1341US2003212973A1Methods for full-chip vectorless dynamic IR analysis in IC designsFiled 2003·Application pending·0 cites
- 1439US2003084353A1System and method for predictive power rampingFiled 2001·Application pending·0 cites
Join the waitlist — get patent alerts
Get an alert when Shen Lin files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →