Inventor · disambiguated record
Darrell D. Boggs
Also filed as: BOGGS DARRELL · BOGGS DARRELL D
50 granted patents·11 pending applications·2,064 citations·filing 1993–2018
99Inventor score
Technology areasG06F
Top patents by PatentIndex Score
61 records- 0197US6385715B1Multi-threading for a processor utilizing a replay queueINTEL CORP·Filed 2001·Granted May 7, 2002·152 cites·29 claims
- 0294US6799268B1Branch ordering bufferINTEL CORP·Filed 2000·Granted Sep 28, 2004·138 cites·19 claims
- 0393US6981129B1Breaking replay dependency loops in a processor using a rescheduled replay queueINTEL CORP·Filed 2000·Granted Dec 27, 2005·87 cites·23 claims
- 0492US10642744B2Memory type which is cacheable yet inaccessible by speculative instructionsNVIDIA CORP·Filed 2018·Granted May 5, 2020·21 cites·24 claims
- 0592US7039794B2Method and apparatus for processing an event occurrence for a least one thread within a multithreaded processorINTEL CORP·Filed 2002·Granted May 2, 2006·64 cites·32 claims
- 0690US9875105B2Checkpointed buffer for re-entry from runaheadROZAS GUILLERMO J·Filed 2012·Granted Jan 23, 2018·20 cites·18 claims
- 0790US6877086B1Method and apparatus for rescheduling multiple micro-operations in a processor using a replay queue and a counterINTEL CORP·Filed 2000·Granted Apr 5, 2005·66 cites·19 claims
- 0890US6496925B1Method and apparatus for processing an event occurrence within a multithreaded processorINTEL CORP·Filed 1999·Granted Dec 17, 2002·117 cites·32 claims
- 0989US6889319B1Method and apparatus for entering and exiting multiple threads within a multithreaded processorINTEL CORP·Filed 1999·Granted May 3, 2005·133 cites·33 claims
- 1088US7181598B2Prediction of load-store dependencies in a processing agentINTEL CORP·Filed 2002·Granted Feb 20, 2007·52 cites·18 claims
- 1187US6651158B2Determination of approaching instruction starvation of threads based on a plurality of conditionsINTEL CORP·Filed 2001·Granted Nov 18, 2003·39 cites·30 claims
- 1286US7849465B2Programmable event driven yield mechanism which may activate service threadsINTEL CORP·Filed 2005·Granted Dec 7, 2010·18 cites·24 claims
- 1385US6735688B1Processor having replay architecture with fast and slow replay pathsINTEL CORP·Filed 2000·Granted May 11, 2004·41 cites·23 claims
- 1484US6041403AMethod and apparatus for generating a microinstruction responsive to the specification of an operand, in addition to a microinstruction based on the opcode, of a macroinstructionINTEL CORP·Filed 1996·Granted Mar 21, 2000·115 cites·34 claims
- 1581US6633970B1Processor with registers storing committed/speculative data and a RAT state history recovery mechanism with retire pointerINTEL CORP·Filed 1999·Granted Oct 14, 2003·83 cites·44 claims
- 1680US9632976B2Lazy runahead operation for a microprocessorNVIDIA CORP·Filed 2012·Granted Apr 25, 2017·5 cites·20 claims
- 1780US7219349B2Multi-threading techniques for a processor utilizing a replay queueINTEL CORP·Filed 2004·Granted May 15, 2007·20 cites·12 claims
- 1878US7353370B2Method and apparatus for processing an event occurrence within a multithreaded processorINTEL CORP·Filed 2005·Granted Apr 1, 2008·6 cites·24 claims
- 1978US5687338AMethod and apparatus for maintaining a macro instruction for refetching in a pipelined processorINTEL CORP·Filed 1995·Granted Nov 11, 1997·81 cites·6 claims
- 2077US7051329B1Method and apparatus for managing resources in a multithreaded processorINTEL CORP·Filed 1999·Granted May 23, 2006·92 cites·15 claims
- 2177US6163838AComputer processor with a replay systemINTEL CORP·Filed 1998·Granted Dec 19, 2000·74 cites·26 claims
- 2275US9563432B2Dynamic configuration of processing pipeline based on determined type of fetched instructionNVIDIA CORP·Filed 2013·Granted Feb 7, 2017·6 cites·16 claims
- 2375US6779103B1Control word register renamingINTEL CORP·Filed 2000·Granted Aug 17, 2004·28 cites·26 claims
- 2475US5463745AMethods and apparatus for determining the next instruction pointer in an out-of-order execution computer systemINTEL CORP·Filed 1993·Granted Oct 31, 1995·66 cites·22 claims
- 2572US7987346B2Method and apparatus for assigning thread priority in a processor or the likeINTEL CORP·Filed 2011·Granted Jul 26, 2011·2 cites·32 claims
- 2672US7454600B2Method and apparatus for assigning thread priority in a processor or the likeINTEL CORP·Filed 2001·Granted Nov 18, 2008·12 cites·12 claims
- 2772US5625788AMicroprocessor with novel instruction for signaling event occurrence and for providing event handling information in response theretoINTEL CORP·Filed 1994·Granted Apr 29, 1997·56 cites·16 claims
- 2871US7010669B2Determining whether thread fetch operation will be blocked due to processing of another threadINTEL CORP·Filed 2003·Granted Mar 7, 2006·13 cites·9 claims
- 2970US6094717AComputer processor with a replay system having a plurality of checkersINTEL CORP·Filed 1998·Granted Jul 25, 2000·55 cites·30 claims
- 3070US5974523AMechanism for efficiently overlapping multiple operand types in a microprocessorINTEL CORP·Filed 1996·Granted Oct 26, 1999·40 cites·27 claims
- 3169US7366879B2Alteration of functional unit partitioning scheme in multithreaded processor based upon thread statusesINTEL CORP·Filed 2004·Granted Apr 29, 2008·12 cites·32 claims
- 3268US7200737B1Processor with a replay system that includes a replay queue for improved throughputINTEL CORP·Filed 1999·Granted Apr 3, 2007·49 cites·26 claims
- 3366US5566298AMethod for state recovery during assist and restart in a decoder having an alias mechanismINTEL CORP·Filed 1994·Granted Oct 15, 1996·50 cites·22 claims
- 3463US7089409B2Interface to a memory system for a processor having a replay systemINTEL CORP·Filed 2003·Granted Aug 8, 2006·7 cites·25 claims
- 3563US6665792B1Interface to a memory system for a processor having a replay systemINTEL CORP·Filed 1999·Granted Dec 16, 2003·35 cites·21 claims
- 3662US6457119B1Processor instruction pipeline with error detection schemeINTEL CORP·Filed 1999·Granted Sep 24, 2002·41 cites·28 claims
- 3761US5537560AMethod and apparatus for conditionally generating a microinstruction that selects one of two values based upon control states of a microprocessorINTEL CORP·Filed 1994·Granted Jul 16, 1996·35 cites·21 claims
- 3859US5740393AInstruction pointer limits in processor that performs speculative out-of-order instruction executionINTEL CORP·Filed 1996·Granted Apr 14, 1998·36 cites·53 claims
- 3956US9891972B2Lazy runahead operation for a microprocessorNVIDIA CORP·Filed 2017·Granted Feb 13, 2018·0 cites·26 claims
- 4055US7877583B2Method and apparatus for assigning thread priority in a processor or the likeINTEL CORP·Filed 2008·Granted Jan 25, 2011·0 cites·22 claims
- 4152US8850165B2Method and apparatus for assigning thread priority in a processor or the likeBURNS DAVID W·Filed 2011·Granted Sep 30, 2014·0 cites·15 claims
- 4251US5581717ADecoding circuit and method providing immediate data for a micro-operation issued from a decoderINTEL CORP·Filed 1994·Granted Dec 3, 1996·22 cites·6 claims
- 4350US7216220B2Microprocessor with customer code storeSTEXAR CORP·Filed 2004·Granted May 8, 2007·4 cites·5 claims
- 4450US6591344B2Method and system for an INUSE field resource management schemeINTEL CORP·Filed 2002·Granted Jul 8, 2003·1 cites·34 claims
- 4549US6026477ABranch recovery mechanism to reduce processor front end stall time by providing path information for both correct and incorrect instructions mixed in the instruction poolINTEL CORP·Filed 1997·Granted Feb 15, 2000·21 cites·17 claims
- 4648US9823931B2Queued instruction re-dispatch after runaheadNVIDIA CORP·Filed 2012·Granted Nov 21, 2017·0 cites·20 claims
- 4748US9740553B2Managing potentially invalid results during runaheadNVIDIA CORP·Filed 2012·Granted Aug 22, 2017·0 cites·20 claims
- 4847US5559974ADecoder having independently loaded micro-alias and macro-alias registers accessible simultaneously by one micro-operationINTEL CORP·Filed 1995·Granted Sep 24, 1996·20 cites·16 claims
- 4946US6467027B1Method and system for an INUSE field resource management schemeINTEL CORP·Filed 1999·Granted Oct 15, 2002·15 cites·22 claims
- 5045US2006015708A1Microprocessor with branch target determination in decoded microinstruction code sequenceBOGGS DARRELL D·Filed 2004·Application pending·0 cites
Showing the top 50 of 61 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →