Inventor · disambiguated record
Luca Gaetano Amaru
Also filed as: AMARU LUCA · AMARU LUCA GAETANO · Amarù Luca Gaetano
12 granted patents·3 pending applications·23 citations·filing 2013–2023
84Inventor score
Files withSYNOPSYS INC11ECOLE POLYTECHNIQUE FED LAUSANNE EPFL2ECOLE POLYTECH1ECOLE POLYTECHNIQUE FED DE LAUSANNE (EPFL)1
Top patents by PatentIndex Score
15 records- 0191US10740517B1Integrated circuit (IC) optimization using Boolean resynthesisSYNOPSYS INC·Filed 2018·Granted Aug 11, 2020·14 cites·9 claims
- 0285US11669665B1Application-specific integrated circuit (ASIC) synthesis based on lookup table (LUT) mapping and optimizationSYNOPSYS INC·Filed 2021·Granted Jun 6, 2023·4 cites·20 claims
- 0371US10839117B1Robust exclusive sum-of-product (ESOP) refactoringSYNOPSYS INC·Filed 2018·Granted Nov 17, 2020·2 cites·12 claims
- 0468US11010511B2Scalable boolean methods in a modern synthesis flowSYNOPSYS INC·Filed 2019·Granted May 18, 2021·1 cites·20 claims
- 0559US10394988B2Majority logic synthesisECOLE POLYTECHNIQUE FED LAUSANNE EPFL·Filed 2014·Granted Aug 27, 2019·1 cites·12 claims
- 0657US9130568B2Controllable polarity FET based arithmetic and differential logicECOLE POLYTECH·Filed 2013·Granted Sep 8, 2015·1 cites·9 claims
- 0752US12175176B2Fast synthesis of logical circuit design with predictive timingSYNOPSYS INC·Filed 2022·Granted Dec 24, 2024·0 cites·17 claims
- 0849US11120184B2Satisfiability sweeping for synthesisSYNOPSYS INC·Filed 2020·Granted Sep 14, 2021·0 cites·20 claims
- 0948US2024078366A1Circuit design adjustments using redundant nodesSYNOPSYS INC·Filed 2023·Application pending·0 cites
- 1046US2023351082A1Satisfiability-based resubstitution for incremental mapped optimizationSYNOPSYS INC·Filed 2023·Application pending·0 cites
- 1145US10325051B2Exact delay synthesisSYNOPSYS INC·Filed 2018·Granted Jun 18, 2019·0 cites·12 claims
- 1243US10049174B2Exact delay synthesisSYNOPSYS INC·Filed 2016·Granted Aug 14, 2018·0 cites·20 claims
- 1342US9685959B2Method for speeding up boolean satisfiabilityECOLE POLYTECHNIQUE FED DE LAUSANNE (EPFL)·Filed 2015·Granted Jun 20, 2017·0 cites·4 claims
- 1438US2022198109A1Boolean methods for engineering change order (eco) patch identificationSYNOPSYS INC·Filed 2021·Application pending·0 cites
- 1536US10380309B2Boolean logic optimization in majority-inverter graphsECOLE POLYTECHNIQUE FED LAUSANNE EPFL·Filed 2015·Granted Aug 13, 2019·0 cites·4 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →