Inventor · disambiguated record
Reid James Riedlinger
Also filed as: RIEDLINGER REID · RIEDLINGER REID J · RIEDLINGER REID JAMES
23 granted patents·2 pending applications·386 citations·filing 2000–2020
96Inventor score
Top patents by PatentIndex Score
25 records- 0192US7590509B2System and method for testing a processorHEWLETT PACKARD DEVELOPMENT CO·Filed 2005·Granted Sep 15, 2009·23 cites·28 claims
- 0289US9075614B2Managing power consumption in a multi-core processorINTEL CORP·Filed 2013·Granted Jul 7, 2015·12 cites·11 claims
- 0388US8020038B2System and method for adjusting operating points of a processor based on detected processor errorsHEWLETT PACKARD DEVELOPMENT CO·Filed 2006·Granted Sep 13, 2011·21 cites·15 claims
- 0487US6539457B1Cache address conflict mechanism without store buffersHEWLETT PACKARD CO·Filed 2000·Granted Mar 25, 2003·58 cites·22 claims
- 0580US6557078B1Cache chain structure to implement high bandwidth low latency cache memory subsystemHEWLETT PACKARD DEVELOPMENT CO·Filed 2000·Granted Apr 29, 2003·32 cites·25 claims
- 0678US11403194B2Systems and methods for in-field core failoverINTEL CORP·Filed 2020·Granted Aug 2, 2022·1 cites·20 claims
- 0778US6507892B1L1 cache memoryHEWLETT PACKARD CO·Filed 2000·Granted Jan 14, 2003·28 cites·18 claims
- 0877US6226217B1Register structure with a dual-ended write mechanismHEWLETT PACKARD CO·Filed 2000·Granted May 1, 2001·24 cites·20 claims
- 0976US6427189B1Multiple issue algorithm with over subscription avoidance feature to get high bandwidth through cache pipelineHEWLETT PACKARD CO·Filed 2000·Granted Jul 30, 2002·25 cites·20 claims
- 1075US6446187B1Virtual address bypassing using local page maskHEWLETT PACKARD CO·Filed 2000·Granted Sep 3, 2002·27 cites·4 claims
- 1174US6539466B1System and method for TLB buddy entry self-timingHEWLETT PACKARD CO·Filed 2000·Granted Mar 25, 2003·22 cites·18 claims
- 1272US6873565B1Dual-ported read SRAM cell with improved soft error immunityHEWLETT PACKARD DEVELOPMENT CO·Filed 2003·Granted Mar 29, 2005·29 cites·12 claims
- 1372US6192001B1Integrated weak write test mode (WWWTM)HEWLETT PACKARD CO·Filed 2000·Granted Feb 20, 2001·19 cites·19 claims
- 1471US10552270B2Systems and methods for in-field core failoverINTEL CORP·Filed 2016·Granted Feb 4, 2020·1 cites·19 claims
- 1570US6550034B1Built-in self test for content addressable memoryHEWLETT PACKARD DEVELOPMENT CO·Filed 2000·Granted Apr 15, 2003·18 cites·20 claims
- 1666US6647464B2System and method utilizing speculative cache access for improved performanceHEWLETT PACKARD DEVELOPMENT CO·Filed 2000·Granted Nov 11, 2003·13 cites·32 claims
- 1763US6208565B1Multi-ported register structure utilizing a pulse write mechanismHEWLETT PACKARD CO·Filed 2000·Granted Mar 27, 2001·13 cites·20 claims
- 1861US8423832B2System and method for preventing processor errorsRIEDLINGER REID J·Filed 2006·Granted Apr 16, 2013·5 cites·20 claims
- 1945US6459304B1Latching annihilation based logic gateHEWLETT PACKARD CO·Filed 2000·Granted Oct 1, 2002·3 cites·10 claims
- 2045US6285579B1System and method for enabling/disabling SRAM banks for memory accessHEWLETT PACKARD CO·Filed 2000·Granted Sep 4, 2001·4 cites·20 claims
- 2141US7146457B2Content addressable memory selectively addressable in a physical address mode and a virtual address modeHEWLETT PACKARD DEVELOPMENT CO·Filed 2003·Granted Dec 5, 2006·5 cites·21 claims
- 2240US2003163643A1Bank conflict determinationFiled 2002·Application pending·0 cites
- 2338US7698673B2Circuit and circuit design methodHEWLETT PACKARD DEVELOPMENT CO·Filed 2004·Granted Apr 13, 2010·3 cites·13 claims
- 2435US6583650B2Latching annihilation based logic gateHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Jun 24, 2003·0 cites·23 claims
- 2521US2004053510A1System for and method of unlimited voltage multi ported sram cellsFiled 2002·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →