Inventor · disambiguated record
James C. Gregerson
Also filed as: GREGERSON JAMES · GREGERSON JAMES C · GREGERSON JAMES CHARLES
11 granted patents·3 pending applications·118 citations·filing 1992–2018
89Inventor score
Technology areasG06F
Top patents by PatentIndex Score
14 records- 0187US9318171B2Dual asynchronous and synchronous memory systemIBM·Filed 2014·Granted Apr 19, 2016·8 cites·12 claims
- 0287US9142272B2Dual asynchronous and synchronous memory systemIBM·Filed 2013·Granted Sep 22, 2015·9 cites·8 claims
- 0384US9542524B2Static timing analysis (STA) using derived boundary timing constraints for out-of-context (OOC) hierarchical entity analysis and abstractionIBM·Filed 2015·Granted Jan 10, 2017·5 cites·18 claims
- 0479US8560989B2Statistical clock cycle computationBUCK NATHAN·Filed 2011·Granted Oct 15, 2013·6 cites·20 claims
- 0578US7873926B2Methods for practical worst test definition and debug during block based statistical static timing analysisIBM·Filed 2008·Granted Jan 18, 2011·9 cites·2 claims
- 0677US7694254B2Method, computer program product, and apparatus for static timing with run-time reductionIBM·Filed 2007·Granted Apr 6, 2010·8 cites·20 claims
- 0774US8458632B2Efficient slack projection for truncated distributionsFOREMAN ERIC A·Filed 2011·Granted Jun 4, 2013·4 cites·20 claims
- 0874US8086988B2Chip design and fabrication method optimized for profitBUCK NATHAN·Filed 2009·Granted Dec 27, 2011·7 cites·25 claims
- 0968US5758342AClient server based multi-processor file system wherein client files written to by a client processor are invisible to the serverIBM·Filed 1995·Granted May 26, 1998·59 cites·26 claims
- 1050US10691853B2Superposition of canonical timing value representations in statistical static timing analysisIBM·Filed 2018·Granted Jun 23, 2020·0 cites·20 claims
- 1149US2017061067A1Timing window manipulation for noise reductionIBM·Filed 2016·Application pending·0 cites
- 1247US2017061059A1Timing window manipulation for noise reductionIBM·Filed 2015·Application pending·0 cites
- 1341US2008307374A1Method, system, and computer program product for mapping a logical design onto an integrated circuit with slack apportionmentIBM·Filed 2007·Application pending·0 cites
- 1428US5446913AMethod and system for nonsequential execution of intermixed scalar and vector instructions in a data processing system utilizing a finish instruction arrayIBM·Filed 1992·Granted Aug 29, 1995·3 cites·6 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →