Inventor · disambiguated record
Sean Xuan Lin
Also filed as: LIN SEAN · LIN SEAN X · LIN SEAN XUAN
34 granted patents·4 pending applications·215 citations·filing 2012–2021
97Inventor score
Files withGLOBALFOUNDRIES INC29ILLINOIS TOOL WORKS2INTERMOLECULAR INC2LIN SEAN X2DERMATOPATHOLOGY LABORATORY OF CENTRAL STATES INC1
Top patents by PatentIndex Score
38 records- 0197US10026687B1Metal interconnects for super (skip) via integrationGLOBALFOUNDRIES INC·Filed 2017·Granted Jul 17, 2018·20 cites·8 claims
- 0297US9805972B1Skip via structuresGLOBALFOUNDRIES INC·Filed 2017·Granted Oct 31, 2017·36 cites·20 claims
- 0395US9853110B2Method of forming a gate contact structure for a semiconductor deviceGLOBALFOUNDRIES INC·Filed 2015·Granted Dec 26, 2017·13 cites·18 claims
- 0494US9520321B2Integrated circuits and methods for fabricating integrated circuits with self-aligned viasGLOBALFOUNDRIES INC·Filed 2015·Granted Dec 13, 2016·11 cites·16 claims
- 0592US10395926B1Multiple patterning with mandrel cuts formed using a block maskGLOBALFOUNDRIES INC·Filed 2018·Granted Aug 27, 2019·11 cites·20 claims
- 0692US10109490B1Cobalt interconnects formed by selective bottom-up fillGLOBALFOUNDRIES INC·Filed 2017·Granted Oct 23, 2018·8 cites·18 claims
- 0791US8778789B2Methods for fabricating integrated circuits having low resistance metal gate structuresGLOBALFOUNDRIES INC·Filed 2012·Granted Jul 15, 2014·13 cites·20 claims
- 0890US10134580B1Metallization levels and methods of making thereofGLOBALFOUNDRIES INC·Filed 2017·Granted Nov 20, 2018·6 cites·17 claims
- 0989US10181421B1Liner recess for fully aligned viaGLOBALFOUNDRIES INC·Filed 2017·Granted Jan 15, 2019·6 cites·15 claims
- 1089US8753975B1Methods of forming conductive copper-based structures using a copper-based nitride seed layer without a barrier layer and the resulting deviceGLOBALFOUNDRIES INC·Filed 2013·Granted Jun 17, 2014·10 cites·21 claims
- 1189US8517769B1Methods of forming copper-based conductive structures on an integrated circuit deviceLIN SEAN X·Filed 2012·Granted Aug 27, 2013·14 cites·41 claims
- 1287US9425103B2Methods of using a metal protection layer to form replacement gate structures for semiconductor devicesGLOBALFOUNDRIES INC·Filed 2014·Granted Aug 23, 2016·7 cites·15 claims
- 1387US8907483B2Semiconductor device having a self-forming barrier layer at via bottomGLOBALFOUNDRIES INC·Filed 2012·Granted Dec 9, 2014·7 cites·19 claims
- 1486US9299745B2Integrated circuits having magnetic tunnel junctions (MTJ) and methods for fabricating the sameGLOBALFOUNDRIES INC·Filed 2014·Granted Mar 29, 2016·5 cites·18 claims
- 1584US10573593B2Metal interconnects for super (skip) via integrationGLOBALFOUNDRIES INC·Filed 2018·Granted Feb 25, 2020·3 cites·12 claims
- 1683US11619597B2Dual robot control systems for non-destructive evaluationILLINOIS TOOL WORKS·Filed 2020·Granted Apr 4, 2023·2 cites·18 claims
- 1782US10580696B1Interconnects formed by a metal displacement reactionGLOBALFOUNDRIES INC·Filed 2018·Granted Mar 3, 2020·3 cites·20 claims
- 1882US8932934B2Methods of self-forming barrier integration with pore stuffed ULK materialGLOBALFOUNDRIES INC·Filed 2013·Granted Jan 13, 2015·6 cites·13 claims
- 1979US8691689B1Methods for fabricating integrated circuits having low resistance device contactsGLOBALFOUNDRIES INC·Filed 2012·Granted Apr 8, 2014·5 cites·20 claims
- 2077US9087881B2Electroless fill of trench in semiconductor structureGLOBALFOUNDRIES INC·Filed 2013·Granted Jul 21, 2015·4 cites·12 claims
- 2176US9054052B2Methods for integration of pore stuffing materialGLOBALFOUNDRIES INC·Filed 2013·Granted Jun 9, 2015·3 cites·17 claims
- 2273US9439565B1Wireless viewing of digital pathology specimensDERMATOPATHOLOGY LABORATORY OF CENTRAL STATES INC·Filed 2013·Granted Sep 13, 2016·15 cites·39 claims
- 2370US9831100B2Solution based etching of titanium carbide and titanium nitride structuresINTERMOLECULAR INC·Filed 2014·Granted Nov 28, 2017·2 cites·18 claims
- 2464US9263327B2Minimizing void formation in semiconductor vias and trenchesGLOBALFOUNDRIES INC·Filed 2014·Granted Feb 16, 2016·1 cites·17 claims
- 2564US8859419B2Methods of forming copper-based nitride liner/passivation layers for conductive copper structures and the resulting deviceGLOBALFOUNDRIES INC·Filed 2013·Granted Oct 14, 2014·1 cites·15 claims
- 2664US8673766B2Methods of forming copper-based conductive structures by forming a copper-based seed layer having an as-deposited thickness profile and thereafter performing an etching process and electroless copper depositionLIN SEAN X·Filed 2012·Granted Mar 18, 2014·2 cites·18 claims
- 2763US10103029B2Process for filling vias in the microelectronicsMACDERMID ENTHONE INC·Filed 2016·Granted Oct 16, 2018·1 cites·27 claims
- 2862USRE49820ESemiconductor device having a self-forming barrier layer at via bottomGLOBALFOUNDRIES INC·Filed 2019·Granted Jan 30, 2024·0 cites·39 claims
- 2956US9318436B2Copper based nitride liner passivation layers for conductive copper structuresGLOBALFOUNDRIES INC·Filed 2014·Granted Apr 19, 2016·0 cites·10 claims
- 3055USRE47630ESemiconductor device having a self-forming barrier layer at via bottomGLOBALFOUNDRIES INC·Filed 2016·Granted Oct 1, 2019·0 cites·19 claims
- 3150US10727120B2Controlling back-end-of-line dimensions of semiconductor devicesGLOBALFOUNDRIES INC·Filed 2018·Granted Jul 28, 2020·0 cites·14 claims
- 3250US10283372B2Interconnects formed by a metal replacement processGLOBALFOUNDRIES INC·Filed 2017·Granted May 7, 2019·0 cites·20 claims
- 3346US2016181087A1Particle removal with minimal etching of silicon-germaniumINTERMOLECULAR INC·Filed 2014·Application pending·0 cites
- 3445US12346412B2Interfaces for assisted defect recognition systemsILLINOIS TOOL WORKS·Filed 2021·Granted Jul 1, 2025·0 cites·16 claims
- 3542US2014353805A1Methods of semiconductor contaminant removal using supercritical fluidGLOBALFOUNDRIES INC·Filed 2013·Application pending·0 cites
- 3641US10879098B2Semiconductor chip holderTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2018·Granted Dec 29, 2020·0 cites·18 claims
- 3738US2018308752A1Middle-of-line local interconnect structures with hybrid featuresGLOBALFOUNDRIES INC·Filed 2017·Application pending·0 cites
- 3834US2017154816A1Amorphous metal interconnections by subtractive etchGLOBALFOUNDRIES INC·Filed 2015·Application pending·0 cites
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →