Inventor · disambiguated record
Boris S. Alvarez-Heredia
Also filed as: ALVAREZ-HEREDIA BORIS S · ALVAREZ-HEREDIA BORIS SIRA
6 granted patents·1 pending application·4 citations·filing 2007–2024
71Inventor score
Top patents by PatentIndex Score
7 records- 0184US11429555B2Coprocessors with bypass optimization, variable grid architecture, and fused vector operationsAPPLE INC·Filed 2019·Granted Aug 30, 2022·3 cites·22 claims
- 0281US2025094381A1Coprocessors with Bypass Optimization, Variable Grid Architecture, and Fused Vector OperationsAPPLE INC·Filed 2024·Application pending·0 cites
- 0373US12174785B2Coprocessors with bypass optimization, variable grid architecture, and fused vector operationsAPPLE INC·Filed 2022·Granted Dec 24, 2024·0 cites·20 claims
- 0473US12135681B2Coprocessors with bypass optimization, variable grid architecture, and fused vector operationsAPPLE INC·Filed 2022·Granted Nov 5, 2024·0 cites·18 claims
- 0565US10969858B2Operation processing controlled according to difference in current consumptionAPPLE INC·Filed 2019·Granted Apr 6, 2021·1 cites·20 claims
- 0646US9645791B2Multiplier unit with speculative rounding for use with division and square-root operationsAPPLE INC·Filed 2014·Granted May 9, 2017·0 cites·20 claims
- 0745US7984269B2Data processing apparatus and method for reducing issue circuitry responsibility by using a predetermined pipeline stage to schedule a next operation in a sequence of operations defined by a complex instructionADVANCED RISC MACH LTD·Filed 2007·Granted Jul 19, 2011·0 cites·16 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →