Inventor · disambiguated record
Chad A. Adams
Also filed as: ADAMS CHAD · ADAMS CHAD A · ADAMS CHAD ALLEN
49 granted patents·8 pending applications·369 citations·filing 2001–2019
98Inventor score
Top patents by PatentIndex Score
57 records- 0195US8279687B2Single supply sub VDD bit-line precharge SRAM and method for level shiftingADAMS CHAD A·Filed 2010·Granted Oct 2, 2012·31 cites·20 claims
- 0294US8233342B2Apparatus and method for implementing write assist for static random access memory arraysADAMS CHAD A·Filed 2008·Granted Jul 31, 2012·43 cites·20 claims
- 0393US8593890B2Implementing supply and source write assist for SRAM arraysADAMS CHAD A·Filed 2012·Granted Nov 26, 2013·31 cites·20 claims
- 0490US9087607B2Implementing sense amplifier for sensing local write driver with bootstrap write assist for SRAM arraysIBM·Filed 2013·Granted Jul 21, 2015·15 cites·18 claims
- 0590US8331180B2Active bit line droop for read assistADAMS CHAD ALLEN·Filed 2010·Granted Dec 11, 2012·21 cites·7 claims
- 0689US6657886B1Split local and continuous bitline for fast domino read SRAMIBM·Filed 2002·Granted Dec 2, 2003·52 cites·11 claims
- 0786US7827018B2Method and computer program for selecting circuit repairs using redundant elements with consideration of aging effectsIBM·Filed 2007·Granted Nov 2, 2010·18 cites·20 claims
- 0882US7817481B2Column selectable self-biasing virtual voltages for SRAM write assistIBM·Filed 2008·Granted Oct 19, 2010·13 cites·14 claims
- 0982US7505340B1Method for implementing SRAM cell write performance evaluationIBM·Filed 2007·Granted Mar 17, 2009·10 cites·6 claims
- 1079US10381098B2Memory interface latch with integrated write-through and fence functionsIBM·Filed 2017·Granted Aug 13, 2019·2 cites·18 claims
- 1178US10229748B1Memory interface latch with integrated write-through functionIBM·Filed 2017·Granted Mar 12, 2019·4 cites·18 claims
- 1278US7609542B2Implementing enhanced SRAM read performance sort ring oscillator (PSRO)IBM·Filed 2007·Granted Oct 27, 2009·10 cites·19 claims
- 1375US7480170B1Method and apparatus for implementing enhanced SRAM read performance sort ring oscillator (PSRO)IBM·Filed 2007·Granted Jan 20, 2009·9 cites·20 claims
- 1475US6901003B2Lower power and reduced device split local and continuous bitline for domino read SRAMsIBM·Filed 2003·Granted May 31, 2005·21 cites·20 claims
- 1573US7724586B2Implementing local evaluation of domino read SRAM with enhanced SRAM cell stability with minimized area usageIBM·Filed 2008·Granted May 25, 2010·8 cites·18 claims
- 1673US7684263B2Method and circuit for implementing enhanced SRAM write and read performance ring oscillatorIBM·Filed 2008·Granted Mar 23, 2010·8 cites·16 claims
- 1769US7506282B2Apparatus and methods for predicting and/or calibrating memory yieldsIBM·Filed 2005·Granted Mar 17, 2009·4 cites·20 claims
- 1867US7289370B2Methods and apparatus for accessing memoryIBM·Filed 2005·Granted Oct 30, 2007·6 cites·16 claims
- 1966US9183896B1Deep sleep wakeup of multi-bank memoryIBM·Filed 2014·Granted Nov 10, 2015·3 cites·4 claims
- 2066US7035127B1Method and sum addressed cell encoder for enhanced compare and search timing for CAM compareIBM·Filed 2004·Granted Apr 25, 2006·14 cites·16 claims
- 2163US7133320B2Flood mode implementation for continuous bitline local evaluation circuitIBM·Filed 2004·Granted Nov 7, 2006·11 cites·19 claims
- 2262US9007857B2SRAM global precharge, discharge, and senseIBM·Filed 2012·Granted Apr 14, 2015·2 cites·10 claims
- 2362US8725622B2System and method for conducting electronic auctions with multi-parameter optimal biddingGUJRAL VIRIND S·Filed 2007·Granted May 13, 2014·2 cites·15 claims
- 2461US7788554B2Design structure embodied in a machine readable medium for implementing SRAM cell write performance evaluationIBM·Filed 2007·Granted Aug 31, 2010·3 cites·16 claims
- 2561US7239559B2Methods and apparatus for accessing memoryIBM·Filed 2005·Granted Jul 3, 2007·4 cites·20 claims
- 2660US7835176B2Implementing enhanced dual mode SRAM performance screen ring oscillatorIBM·Filed 2009·Granted Nov 16, 2010·4 cites·20 claims
- 2759US8274848B2Level shifter for use with memory arraysADAMS CHAD A·Filed 2010·Granted Sep 25, 2012·2 cites·20 claims
- 2857US7751266B2High performance read bypass test for SRAM circuitsIBM·Filed 2008·Granted Jul 6, 2010·3 cites·18 claims
- 2957US7224594B2Glitch protect valid cell and method for maintaining a desired state valueIBM·Filed 2005·Granted May 29, 2007·4 cites·20 claims
- 3053US9251869B2Deep sleep wakeup of multi-bank memoryIBM·Filed 2014·Granted Feb 2, 2016·0 cites·4 claims
- 3153US7400550B2Delay mechanism for unbalanced read/write paths in domino SRAM arraysIBM·Filed 2006·Granted Jul 15, 2008·2 cites·3 claims
- 3252US7983080B2Non-body contacted sense amplifier with negligible history effectIBM·Filed 2009·Granted Jul 19, 2011·2 cites·19 claims
- 3352US7760541B2Functional float mode screen to test for leakage defects on SRAM bitlinesIBM·Filed 2008·Granted Jul 20, 2010·2 cites·8 claims
- 3451US7783943B2Method and apparatus for testing a random access memory deviceIBM·Filed 2008·Granted Aug 24, 2010·2 cites·1 claims
- 3549US10916323B2Memory interface latch with integrated write-through and fence functionsIBM·Filed 2019·Granted Feb 9, 2021·0 cites·18 claims
- 3649US7768851B2Apparatus for implementing SRAM cell write performance evaluationIBM·Filed 2009·Granted Aug 3, 2010·1 cites·13 claims
- 3747US8108739B2High-speed testing of integrated devicesADAMS CHAD A·Filed 2008·Granted Jan 31, 2012·1 cites·21 claims
- 3847US2002042769A1System and method for conducting electronic auctions with multi-parameter optimal biddingFiled 2001·Application pending·0 cites
- 3944US10060343B2Air flow system for an enclosed portable generatorGENERAC POWER SYSTEMS INC·Filed 2015·Granted Aug 28, 2018·0 cites·18 claims
- 4043US9007858B2SRAM global precharge, discharge, and senseIBM·Filed 2013·Granted Apr 14, 2015·0 cites·4 claims
- 4142US8754691B2Memory array pulse width controlIBM·Filed 2013·Granted Jun 17, 2014·0 cites·19 claims
- 4242US8213249B2Implementing low power data predicting local evaluation for double pumped arraysADAMS CHAD ALLEN·Filed 2010·Granted Jul 3, 2012·0 cites·20 claims
- 4342US7860172B2Self clock generation structure for low power local clock buffering decoderIBM·Filed 2004·Granted Dec 28, 2010·0 cites·16 claims
- 4442US2014149818A1Diagnostic testing for a double-pumped memory arrayIBM·Filed 2013·Application pending·0 cites
- 4542US2014149817A1Diagnostic testing for a double-pumped memory arrayIBM·Filed 2012·Application pending·0 cites
- 4642US2007043895A1Method and apparatus for row based power control of a microprocessor memory arrayADAMS CHAD A·Filed 2005·Application pending·0 cites
- 4741US2008212396A1Delay Mechanism for Unbalanced Read/Write Paths in Domino SRAM ArraysIBM·Filed 2008·Application pending·0 cites
- 4840US7283411B2Flood mode implementation for continuous bitline local evaluation circuitIBM·Filed 2006·Granted Oct 16, 2007·0 cites·20 claims
- 4940US7015600B2Pulse generator circuit and semiconductor device including sameIBM·Filed 2002·Granted Mar 21, 2006·1 cites·16 claims
- 5039US8659937B2Implementing low power write disabled local evaluation for SRAMADAMS CHAD A·Filed 2012·Granted Feb 25, 2014·0 cites·20 claims
Showing the top 50 of 57 patent records by PatentIndex Score.
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