Inventor · disambiguated record
Yongzhong Hu
Also filed as: HU YONGZHONG
26 granted patents·6 pending applications·316 citations·filing 1999–2024
96Inventor score
Files withALPHA & OMEGA SEMICONDUCTOR9ADVANCED MICRO DEVICES INC6LATTICE SEMICONDUCTOR CORP5HU YONGZHONG4RICHTEK TECHNOLOGY CORP2
Top patents by PatentIndex Score
32 records- 0196US7256446B2One time programmable memory cellALPHA & OMEGA SEMICONDUCTOR·Filed 2005·Granted Aug 14, 2007·38 cites·15 claims
- 0293US6271087B1Method for forming self-aligned contacts and local interconnects using self-aligned local interconnectsADVANCED MICRO DEVICES INC·Filed 2000·Granted Aug 7, 2001·74 cites·18 claims
- 0388US9337329B2Method of fabrication and device configuration of asymmetrical DMOSFET with schottky barrier sourceHU YONGZHONG·Filed 2011·Granted May 10, 2016·9 cites·15 claims
- 0484US6306713B1Method for forming self-aligned contacts and local interconnects for salicided gates using a secondary spacerADVANCED MICRO DEVICES INC·Filed 2001·Granted Oct 23, 2001·40 cites·20 claims
- 0583US7855422B2Formation of high sheet resistance resistors and high capacitance capacitors by a single polysilicon processALPHA & OMEGA SEMICONDUCTOR·Filed 2006·Granted Dec 21, 2010·9 cites·12 claims
- 0683US6482699B1Method for forming self-aligned contacts and local interconnects using decoupled local interconnect processADVANCED MICRO DEVICES INC·Filed 2000·Granted Nov 19, 2002·37 cites·18 claims
- 0781US9159828B2Top drain LDMOSMALLIKARJUNASWAMY SHEKAR·Filed 2012·Granted Oct 13, 2015·5 cites·14 claims
- 0879US10629474B1Integrated isolation capacitance structureSEMICONDUCTOR COMPONENTS IND LLC·Filed 2019·Granted Apr 21, 2020·2 cites·20 claims
- 0978US7824977B2Completely decoupled high voltage and low voltage transistor manufacturing processesALPHA & OMEGA SEMICONDUCTOR·Filed 2007·Granted Nov 2, 2010·7 cites·3 claims
- 1077US8058687B2Split gate with different gate materials and work functions to reduce gate resistance of ultra high density MOSFETTAI SUNG-SHAN·Filed 2007·Granted Nov 15, 2011·6 cites·14 claims
- 1176US10008598B2Top drain LDMOSALPHA & OMEGA SEMICONDUCTOR·Filed 2015·Granted Jun 26, 2018·2 cites·15 claims
- 1272US7829941B2Configuration and method to form MOSFET devices with low resistance silicide gate and mesa contact regionsALPHA & OMEGA SEMICONDUCTOR·Filed 2006·Granted Nov 9, 2010·3 cites·14 claims
- 1370US8105905B2Configuration and method to form MOSFET devices with low resistance silicide gate and mesa contact regionsHU YONGZHONG·Filed 2010·Granted Jan 31, 2012·2 cites·6 claims
- 1470US6627947B1Compact single-poly two transistor EEPROM cellLATTICE SEMICONDUCTOR CORP·Filed 2000·Granted Sep 30, 2003·16 cites·6 claims
- 1567US6693830B1Single-poly two-transistor EEPROM cell with differentially doped floating gateLATTICE SEMICONDUCTOR CORP·Filed 2001·Granted Feb 17, 2004·15 cites·23 claims
- 1667US6348406B1Method for using a low dielectric constant layer as a semiconductor anti-reflective coatingADVANCED MICRO DEVICES INC·Filed 2000·Granted Feb 19, 2002·11 cites·16 claims
- 1766US8835251B2Formation of high sheet resistance resistors and high capacitance capacitors by a single polysilicon processHU YONGZHONG·Filed 2010·Granted Sep 16, 2014·2 cites·15 claims
- 1864US2025364170A1Inductor module with heat dissipation function and manufacturing method thereofRICHTEK TECHNOLOGY CORP·Filed 2024·Application pending·0 cites
- 1963US6794236B1Eeprom device with improved capacitive coupling and fabrication processLATTICE SEMICONDUCTOR CORP·Filed 2002·Granted Sep 21, 2004·10 cites·14 claims
- 2059US2025311249A1Chip Heat Dissipation Integrated Packaging ModuleRICHTEK TECHNOLOGY CORP·Filed 2024·Application pending·0 cites
- 2158US8022482B2Device configuration of asymmetrical DMOSFET with schottky barrier sourceALPHA & OMEGA SEMICONDUCTOR·Filed 2006·Granted Sep 20, 2011·1 cites·13 claims
- 2258US7805687B2One-time programmable (OTP) memory cellALPHA & OMEGA SEMICONDUCTOR·Filed 2006·Granted Sep 28, 2010·1 cites·22 claims
- 2355US6842372B1EEPROM cell having a floating-gate transistor within a cell well and a process for fabricating the memory cellLATTICE SEMICONDUCTOR CORP·Filed 2002·Granted Jan 11, 2005·8 cites·22 claims
- 2452US8236653B2Configuration and method to form MOSFET devices with low resistance silicide gate and mesa contact regionsHU YONGZHONG·Filed 2012·Granted Aug 7, 2012·0 cites·16 claims
- 2552US6376389B1Method for eliminating anti-reflective coating in semiconductorsADVANCED MICRO DEVICES INC·Filed 2000·Granted Apr 23, 2002·5 cites·8 claims
- 2651US2010015770A1Double gate manufactured with locos techniquesALPHA & OMEGA SEMICONDUCTOR·Filed 2009·Application pending·0 cites
- 2749US8524558B2Split gate with different gate materials and work functions to reduce gate resistance of ultra high density MOSFETTAI SUNG-SHAN·Filed 2011·Granted Sep 3, 2013·0 cites·9 claims
- 2848US6797568B1Flash technology transistors and methods for forming the sameLATTICE SEMICONDUCTOR CORP·Filed 2002·Granted Sep 28, 2004·3 cites·10 claims
- 2948US2008296673A1Double gate manufactured with locos techniquesALPHA & OMEGA SEMICONDUCTOR·Filed 2007·Application pending·0 cites
- 3043US6506683B1In-situ process for fabricating a semiconductor device with integral removal of antireflection and etch stop layersADVANCED MICRO DEVICES INC·Filed 1999·Granted Jan 14, 2003·10 cites·5 claims
- 3140US2006128162A1Process for fabricating a semiconductor device having an RTCVD layerMEHTA SUNIL D·Filed 2004·Application pending·0 cites
- 3237US2006145238A1Diode structure for word-line protection in a memory circuitFONTANA FABIANO·Filed 2005·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →