Inventor · disambiguated record
Hongwen Yan
Also filed as: YAN HONGWEN
39 granted patents·16 pending applications·264 citations·filing 1999–2021
97Inventor score
Top patents by PatentIndex Score
55 records- 0193US11575077B2Microfabricated air bridges for quantum circuitsIBM·Filed 2020·Granted Feb 7, 2023·3 cites·21 claims
- 0290US8018005B2CMOS (complementary metal oxide semiconductor) devices having metal gate NFETs and poly-silicon gate PFETsIBM·Filed 2010·Granted Sep 13, 2011·11 cites·9 claims
- 0389US7691701B1Method of forming gate stack and structure thereofIBM·Filed 2009·Granted Apr 6, 2010·16 cites·27 claims
- 0487US8159040B2Metal gate integration structure and method including metal fuse, anti-fuse and/or resistorCOOLBAUGH DOUGLAS D·Filed 2008·Granted Apr 17, 2012·15 cites·21 claims
- 0585US7820552B2Advanced high-k gate stack patterning and structure containing a patterned high-k gate stackIBM·Filed 2007·Granted Oct 26, 2010·10 cites·31 claims
- 0684US8481389B2Method of removing high-K dielectric layer on sidewalls of gate structureZHANG YING·Filed 2011·Granted Jul 9, 2013·7 cites·16 claims
- 0783US11844290B2Plasma co-doping to reduce the forming voltage in resistive random access memory (ReRAM) devicesTOKYO ELECTRON LTD·Filed 2021·Granted Dec 12, 2023·1 cites·21 claims
- 0883US7671421B2CMOS structure and method for fabrication thereof using multiple crystallographic orientations and gate materialsIBM·Filed 2006·Granted Mar 2, 2010·8 cites·13 claims
- 0983US7435652B1Integration schemes for fabricating polysilicon gate MOSFET and high-K dielectric metal gate MOSFETIBM·Filed 2007·Granted Oct 14, 2008·11 cites·20 claims
- 1083US6838347B1Method for reducing line edge roughness of oxide material using chemical oxide removalIBM·Filed 2003·Granted Jan 4, 2005·28 cites·12 claims
- 1183US6541320B2Method to controllably form notched polysilicon gate structuresIBM·Filed 2001·Granted Apr 1, 2003·32 cites·24 claims
- 1282US10276384B2Plasma shallow doping and wet removal of depth control capIBM·Filed 2017·Granted Apr 30, 2019·2 cites·14 claims
- 1381US8901706B2Thermally stable high-K tetragonal HFO2 layer within high aspect ratio deep trenchesCHUDZIK MICHAEL P·Filed 2012·Granted Dec 2, 2014·4 cites·14 claims
- 1481US8158481B2CMOS structure and method for fabrication thereof using multiple crystallographic orientations and gate materialsCHEN TZE-CHIANG·Filed 2010·Granted Apr 17, 2012·5 cites·8 claims
- 1580US7863123B2Direct contact between high-κ/metal gate and wiring process flowIBM·Filed 2009·Granted Jan 4, 2011·8 cites·20 claims
- 1680US7790559B2Semiconductor transistors having high-K gate dielectric layers and metal gate electrodesIBM·Filed 2008·Granted Sep 7, 2010·7 cites·6 claims
- 1777US8227874B2Semiconductor transistors having high-K gate dielectric layers and metal gate electrodesADKISSON JAMES WILLIAM·Filed 2010·Granted Jul 24, 2012·4 cites·18 claims
- 1877US7329602B2Wiring structure for integrated circuit with reduced intralevel capacitanceIBM·Filed 2005·Granted Feb 12, 2008·6 cites·16 claims
- 1977US6345399B1Hard mask process to prevent surface roughness for selective dielectric etchingIBM·Filed 2000·Granted Feb 12, 2002·20 cites·17 claims
- 2074US8193099B1Protecting exposed metal gate structures from etching processes in integrated circuit manufacturingKHARE MUKESH V·Filed 2011·Granted Jun 5, 2012·4 cites·20 claims
- 2171US6509219B2Fabrication of notched gates by passivating partially etched gate sidewalls and then using an isotropic etchIBM·Filed 2001·Granted Jan 21, 2003·17 cites·32 claims
- 2270US8785281B2CMOS structure and method for fabrication thereof using multiple crystallographic orientations and gate materialsCHEN TZE-CHIANG·Filed 2012·Granted Jul 22, 2014·2 cites·20 claims
- 2366US7863124B2Residue free patterned layer formation method applicable to CMOS structuresIBM·Filed 2007·Granted Jan 4, 2011·2 cites·31 claims
- 2466US7077903B2Etch selectivity enhancement for tunable etch resistant anti-reflective layerIBM·Filed 2003·Granted Jul 18, 2006·9 cites·20 claims
- 2563US9240452B2Array and moat isolation structures and method of manufactureIBM·Filed 2014·Granted Jan 19, 2016·1 cites·15 claims
- 2663US8673737B2Array and moat isolation structures and method of manufactureKUSABA NAOYOSHI·Filed 2011·Granted Mar 18, 2014·2 cites·20 claims
- 2763US7820555B2Method of patterning multilayer metal gate structures for CMOS devicesIBM·Filed 2007·Granted Oct 26, 2010·1 cites·20 claims
- 2863US6908806B2Gate metal recess for oxidation protection and parasitic capacitance reductionIBM·Filed 2003·Granted Jun 21, 2005·10 cites·7 claims
- 2960US7081393B2Reduced dielectric constant spacer materials integration for high speed logic gatesIBM·Filed 2004·Granted Jul 25, 2006·8 cites·20 claims
- 3058US9087927B2Thermally stable high-K tetragonal HFO2 layer within high aspect ratio deep trenchesIBM·Filed 2014·Granted Jul 21, 2015·0 cites·18 claims
- 3156US2018218909A1Plasma shallow doping and wet removal of depth control capIBM·Filed 2018·Application pending·0 cites
- 3256US2018218908A1Plasma shallow doping and wet removal of depth control capIBM·Filed 2018·Application pending·0 cites
- 3353US12048254B2Sacrificial material facilitating protection of a substrate in a qubit deviceIBM·Filed 2020·Granted Jul 23, 2024·0 cites·9 claims
- 3453US8198103B2Addition of ballast hydrocarbon gas to doped polysilicon etch masked by resistDALTON TIMOTHY J·Filed 2008·Granted Jun 12, 2012·0 cites·14 claims
- 3553US2019311945A1Self-aligned trench metal-alloying for iii-v nfetsIBM·Filed 2019·Application pending·0 cites
- 3651US7438822B2Apparatus and method for shielding a wafer from charged particles during plasma etchingIBM·Filed 2005·Granted Oct 21, 2008·0 cites·8 claims
- 3749US7749830B2CMOS (complementary metal oxide semiconductor) devices having metal gate NFETS and poly-silicon gate PFETSIBM·Filed 2008·Granted Jul 6, 2010·0 cites·25 claims
- 3847US11882771B2Smooth metal layers in Josephson junction devicesIBM·Filed 2021·Granted Jan 23, 2024·0 cites·18 claims
- 3947US10366918B2Self-aligned trench metal-alloying for III-V nFETsIBM·Filed 2016·Granted Jul 30, 2019·0 cites·15 claims
- 4047US2006166416A1Addition of ballast hydrocarbon gas to doped polysilicon etch masked by resistIBM·Filed 2005·Application pending·0 cites
- 4146US2009104776A1Methods for forming nested and isolated lines in semiconductor devicesIBM·Filed 2007·Application pending·0 cites
- 4244US2008194112A1Method and system for plasma etching having improved across-wafer etch uniformityIBM·Filed 2007·Application pending·0 cites
- 4343US2009250760A1Methods of forming high-k/metal gates for nfets and pfetsIBM·Filed 2008·Application pending·0 cites
- 4442US11018225B2III-V extension by high temperature plasma dopingIBM·Filed 2016·Granted May 25, 2021·0 cites·10 claims
- 4542US8907405B2Semiconductor structures with dual trench regions and methods of manufacturing the semiconductor structuresVEGA REINALDO A·Filed 2011·Granted Dec 9, 2014·0 cites·29 claims
- 4642US2009152651A1Gate stack structure with oxygen gettering layerIBM·Filed 2007·Application pending·0 cites
- 4741US6294102B1Selective dry etch of a dielectric filmIBM·Filed 1999·Granted Sep 25, 2001·10 cites·18 claims
- 4841US2005239284A1Wiring structure for integrated circuit with reduced intralevel capacitanceIBM·Filed 2004·Application pending·0 cites
- 4941US2004112544A1Magnetic mirror for preventing wafer edge damage during dry etchingFiled 2002·Application pending·0 cites
- 5041US2006154184A1Method for reducing feature line edge roughnessADVANCED MICRO DEVICES INC·Filed 2005·Application pending·0 cites
Showing the top 50 of 55 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →