Inventor · disambiguated record
Donald R. Weiss
Also filed as: WEISS DONALD · WEISS DONALD R
23 granted patents·12 pending applications·407 citations·filing 1996–2014
96Inventor score
Files withHEWLETT PACKARD CO12HEWLETT PACKARD DEVELOPMENT CO4ADVANCED MICRO DEVICES INC3WUU JOHN J3SCHULTZ RICHARD T2
Top patents by PatentIndex Score
35 records- 0190US5986923AMethod and apparatus for improving read/write stability of a single-port SRAM cellHEWLETT PACKARD CO·Filed 1998·Granted Nov 16, 1999·97 cites·8 claims
- 0289US8076236B2SRAM bit cell with self-aligned bidirectional local interconnectsSCHULTZ RICHARD T·Filed 2009·Granted Dec 13, 2011·16 cites·10 claims
- 0387US7430145B2System and method for avoiding attempts to access a defective portion of memoryHEWLETT PACKARD DEVELOPMENT CO·Filed 2005·Granted Sep 30, 2008·27 cites·21 claims
- 0486US6249465B1Redundancy programming using addressable scan paths to reduce the number of required fusesHEWLETT PACKARD CO·Filed 2000·Granted Jun 19, 2001·45 cites·20 claims
- 0582US6363006B2Asymmetric RAM cellHEWLETT PACKARD CO·Filed 2001·Granted Mar 26, 2002·29 cites·21 claims
- 0681US9575891B2Sidecar SRAM for high granularity in floor plan aspect ratioADVANCED MICRO DEVICES INC·Filed 2014·Granted Feb 21, 2017·6 cites·17 claims
- 0779US8276039B2Error detection device and methods thereofWUU JOHN J·Filed 2009·Granted Sep 25, 2012·14 cites·20 claims
- 0877US6240009B1Asymmetric ram cellHEWLETT PACKARD CO·Filed 2000·Granted May 29, 2001·22 cites·25 claims
- 0977US6226217B1Register structure with a dual-ended write mechanismHEWLETT PACKARD CO·Filed 2000·Granted May 1, 2001·24 cites·20 claims
- 1072US6192001B1Integrated weak write test mode (WWWTM)HEWLETT PACKARD CO·Filed 2000·Granted Feb 20, 2001·19 cites·19 claims
- 1171US6366526B2Static random access memory (SRAM) array central global decoder system and methodFiled 2001·Granted Apr 2, 2002·16 cites·33 claims
- 1271US6243287B1Distributed decode system and method for improving static random access memory (SRAM) densityHEWLETT PACKARD CO·Filed 2000·Granted Jun 5, 2001·16 cites·25 claims
- 1370US6550034B1Built-in self test for content addressable memoryHEWLETT PACKARD DEVELOPMENT CO·Filed 2000·Granted Apr 15, 2003·18 cites·20 claims
- 1469US6493855B1Flexible cache architecture using modular arraysHEWLETT PACKARD CO·Filed 2000·Granted Dec 10, 2002·14 cites·18 claims
- 1563US6208565B1Multi-ported register structure utilizing a pulse write mechanismHEWLETT PACKARD CO·Filed 2000·Granted Mar 27, 2001·13 cites·20 claims
- 1661US6292093B1Multi-bit comparatorHEWLETT PACKARD CO·Filed 2000·Granted Sep 18, 2001·10 cites·11 claims
- 1750US7133319B2Programmable weak write test mode (PWWTM) bias generation having logic high output default modeHEWLETT PACKARD DEVELOPMENT CO·Filed 2003·Granted Nov 7, 2006·6 cites·24 claims
- 1847US2012037996A1Sram bit cell with self-aligned bidirectional local interconnectsSCHULTZ RICHARD T·Filed 2011·Application pending·0 cites
- 1945US6285579B1System and method for enabling/disabling SRAM banks for memory accessHEWLETT PACKARD CO·Filed 2000·Granted Sep 4, 2001·4 cites·20 claims
- 2045US2013070513A1Method and apparatus for direct backup of memory circuitsWEISS DONALD R·Filed 2012·Application pending·0 cites
- 2143US8695886B1Memory chip deviceWEISS DONALD·Filed 2013·Granted Apr 15, 2014·0 cites·5 claims
- 2243US2004148559A1Method and circuit for reducing silent data corruption in storage arrays with no increase in read and write timesFiled 2003·Application pending·0 cites
- 2342US7076376B1System and method for calibrating weak write test mode (WWTM)HEWLETT PACKARD DEVELOPMENT CO·Filed 2004·Granted Jul 11, 2006·3 cites·26 claims
- 2442US5787041ASystem and method for improving a random access memory (RAM)HEWLETT PACKARD CO·Filed 1996·Granted Jul 28, 1998·8 cites·17 claims
- 2539US2013070514A1Integrated circuit with on-die distributed programmable passive variable resistance fuse array and method of making sameWEISS DONALD R·Filed 2012·Application pending·0 cites
- 2637US9159409B2Method and apparatus for providing complimentary state retentionADVANCED MICRO DEVICES INC·Filed 2012·Granted Oct 13, 2015·0 cites·17 claims
- 2736US2013083048A1Integrated circuit with active memory and passive variable resistive memory with shared memory control logic and method of making sameADVANCED MICRO DEVICES INC·Filed 2012·Application pending·0 cites
- 2834US7724578B2Sensing device for floating body cell memory and method thereofGLOBALFOUNDRIES INC·Filed 2006·Granted May 25, 2010·0 cites·16 claims
- 2931US2005050400A1Shift redundancy encoding for use with digital memoriesFiled 2003·Application pending·0 cites
- 3031US2004257882A1Bias generation having adjustable range and resolution through metal programmingFiled 2003·Application pending·0 cites
- 3130US2003026135A1Data-shifting scheme for utilizing multiple redundant elementsFiled 2001·Application pending·0 cites
- 3229US2007081409A1Reduced bitline leakage currentWUU JOHN J·Filed 2005·Application pending·0 cites
- 3329US2012173921A1Redundancy memory storage system and a method for controlling a redundancy memory storage systemWUU JOHN J·Filed 2011·Application pending·0 cites
- 3427US2007014137A1Banked cache with multiplexerMELLINGER TODD W·Filed 2005·Application pending·0 cites
- 3526US2006133135A1Reducing power in SRAMs while maintaining cell stabilityLACHMAN JONATHAN E·Filed 2004·Application pending·0 cites
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →