Inventor · disambiguated record
Xiaorong Morrow
Also filed as: MORROW XIAORONG
8 granted patents·1 pending application·142 citations·filing 2001–2010
88Inventor score
Top patents by PatentIndex Score
9 records- 0189US6448177B1Method of making a semiconductor device having a dual damascene interconnect spaced from a support structureINTEL CORP·Filed 2001·Granted Sep 10, 2002·56 cites·8 claims
- 0285US7456490B2Sealing porous dielectrics with silane coupling reagentsINTEL CORP·Filed 2006·Granted Nov 25, 2008·9 cites·7 claims
- 0379US6661094B2Semiconductor device having a dual damascene interconnect spaced from a support structureINTEL CORP·Filed 2002·Granted Dec 9, 2003·25 cites·1 claims
- 0475US7122481B2Sealing porous dielectrics with silane coupling reagentsINTEL CORP·Filed 2003·Granted Oct 17, 2006·15 cites·27 claims
- 0574US7727892B2Method and apparatus for forming metal-metal oxide etch stop/barrier for integrated circuit interconnectsINTEL CORP·Filed 2002·Granted Jun 1, 2010·16 cites·20 claims
- 0670US6794755B2Surface alteration of metal interconnect in integrated circuits for electromigration and adhesion improvementINTEL CORP·Filed 2003·Granted Sep 21, 2004·11 cites·6 claims
- 0764US7339271B2Metal-metal oxide etch stop/barrier for integrated circuit interconnectsINTEL CORP·Filed 2004·Granted Mar 4, 2008·9 cites·19 claims
- 0857US8299617B2Method and apparatus for forming metal-metal oxide etch stop/barrier for integrated circuit interconnectsMORROW XIAORONG·Filed 2010·Granted Oct 30, 2012·1 cites·5 claims
- 0940US2004056366A1A method of forming surface alteration of metal interconnect in integrated circuits for electromigration and adhesion improvementFiled 2002·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →