Inventor · disambiguated record
Derwin Jallice
Also filed as: JALLICE DERWIN · JALLICE DERWIN L
10 granted patents·255 citations·filing 1989–2010
91Inventor score
Top patents by PatentIndex Score
10 records- 0194US7692946B2Memory array on more than one dieINTEL CORP·Filed 2007·Granted Apr 6, 2010·40 cites·22 claims
- 0285US6275080B1Enhanced single event upset immune latch circuitBAE SYSTEMS·Filed 2000·Granted Aug 14, 2001·49 cites·22 claims
- 0382US5117129ACmos off chip driver for fault tolerant cold sparingIBM·Filed 1990·Granted May 26, 1992·61 cites·2 claims
- 0470US6208554B1Single event upset (SEU) hardened static random access memory cellLOCKHEED CORP·Filed 1999·Granted Mar 27, 2001·30 cites·35 claims
- 0566US6285580B1Method and apparatus for hardening a static random access memory cell from single event upsetsBAE SYSTEMS INFORMATION·Filed 1999·Granted Sep 4, 2001·26 cites·26 claims
- 0665US8059441B2Memory array on more than one dieTAUFIQUE MOHAMMED H·Filed 2010·Granted Nov 15, 2011·2 cites·22 claims
- 0761US4996670AZero standby power, radiation hardened, memory redundancy circuitIBM·Filed 1989·Granted Feb 26, 1991·18 cites·3 claims
- 0851US5146111AGlitch-proof powered-down on chip receiver with non-overlapping outputsIBM·Filed 1991·Granted Sep 8, 1992·11 cites·1 claims
- 0945US5301165AChip select speedup circuit for a memoryIBM·Filed 1992·Granted Apr 5, 1994·10 cites·6 claims
- 1041US5592426AExtended segmented precharge architectureIBM·Filed 1995·Granted Jan 7, 1997·8 cites·4 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →