Inventor · disambiguated record
Kiyohiko Sakakibara
Also filed as: SAKAKIBARA KIYOHIKO
52 granted patents·6 pending applications·1,066 citations·filing 1990–2022
99Inventor score
Files withSANDISK TECHNOLOGIES LLC26MITSUBISHI ELECTRIC CORP16RENESAS TECH CORP7SANDISK TECHNOLOGIES INC6KASAOKA TATSUO1
Top patents by PatentIndex Score
58 records- 0199US10304852B1Three-dimensional memory device containing through-memory-level contact via structuresSANDISK TECHNOLOGIES LLC·Filed 2018·Granted May 28, 2019·115 cites·12 claims
- 0298US10199359B1Three-dimensional memory device employing direct source contact and hole current detection and method of making the sameSANDISK TECHNOLOGIES LLC·Filed 2017·Granted Feb 5, 2019·88 cites·11 claims
- 0398US9356043B1Three-dimensional memory devices containing memory stack structures with position-independent threshold voltageSANDISK TECHNOLOGIES INC·Filed 2015·Granted May 31, 2016·62 cites·21 claims
- 0497US10854627B1Three-dimensional memory device containing a capped insulating source line core and method of making the sameSANDISK TECHNOLOGIES LLC·Filed 2018·Granted Dec 1, 2020·29 cites·10 claims
- 0597US10777575B1Three-dimensional memory device with self-aligned vertical conductive strips having a gate-all-around configuration and method of making the sameSANDISK TECHNOLOGIES LLC·Filed 2019·Granted Sep 15, 2020·24 cites·11 claims
- 0697US10720445B1Three-dimensional memory device having nitrided direct source strap contacts and method of making thereofSANDISK TECHNOLOGIES LLC·Filed 2018·Granted Jul 21, 2020·45 cites·11 claims
- 0797US10629613B1Three-dimensional memory device having vertical semiconductor channels including source-side boron-doped pockets and methods of making the sameSANDISK TECHNOLOGIES LLC·Filed 2018·Granted Apr 21, 2020·41 cites·11 claims
- 0897US9443866B1Mid-tunneling dielectric band gap modification for enhanced data retention in a three-dimensional semiconductor deviceSANDISK TECHNOLOGIES INC·Filed 2015·Granted Sep 13, 2016·22 cites·30 claims
- 0996US10903222B2Three-dimensional memory device containing a carbon-doped source contact layer and methods for making the sameSANDISK TECHNOLOGIES LLC·Filed 2019·Granted Jan 26, 2021·13 cites·16 claims
- 1095US10916556B1Three-dimensional memory device using a buried source line with a thin semiconductor oxide tunneling layerSANDISK TECHNOLOGIES LLC·Filed 2018·Granted Feb 9, 2021·24 cites·10 claims
- 1195US10720444B2Three-dimensional flat memory device including a dual dipole blocking dielectric layer and methods of making the sameSANDISK TECHNOLOGIES LLC·Filed 2018·Granted Jul 21, 2020·9 cites·11 claims
- 1295US10586803B2Three-dimensional memory device and methods of making the same using replacement drain select gate electrodesSANDISK TECHNOLOGIES LLC·Filed 2018·Granted Mar 10, 2020·9 cites·10 claims
- 1395US9711530B1Locally-trap-characteristic-enhanced charge trap layer for three-dimensional memory structuresSANDISK TECHNOLOGIES LLC·Filed 2016·Granted Jul 18, 2017·23 cites·14 claims
- 1494US9601508B2Blocking oxide in memory opening integration scheme for three-dimensional memory structureSANDISK TECHNOLOGIES INC·Filed 2015·Granted Mar 21, 2017·11 cites·15 claims
- 1594US9589839B1Method of reducing control gate electrode curvature in three-dimensional memory devicesSANDISK TECHNOLOGIES INC·Filed 2016·Granted Mar 7, 2017·19 cites·23 claims
- 1693US9666281B2Three-dimensional P-I-N memory device and method reading thereof using hole current detectionSANDISK TECHNOLOGIES INC·Filed 2015·Granted May 30, 2017·15 cites·10 claims
- 1792US10381229B2Three-dimensional memory device with straddling drain select electrode lines and method of making thereofSANDISK TECHNOLOGIES LLC·Filed 2017·Granted Aug 13, 2019·9 cites·12 claims
- 1892US10074661B2Three-dimensional junction memory device and method reading thereof using hole current detectionSANDISK TECHNOLOGIES LLC·Filed 2016·Granted Sep 11, 2018·12 cites·21 claims
- 1992US9911748B2Epitaxial source region for uniform threshold voltage of vertical transistors in 3D memory devicesSANDISK TECHNOLOGIES INC·Filed 2015·Granted Mar 6, 2018·8 cites·19 claims
- 2090US6445617B1Non-volatile semiconductor memory and methods of driving, operating, and manufacturing this memoryMITSUBISHI ELECTRIC CORP·Filed 2000·Granted Sep 3, 2002·49 cites·8 claims
- 2190US6172397B1Non-volatile semiconductor memory deviceMITSUBISHI ELECTRIC CORP·Filed 1998·Granted Jan 9, 2001·83 cites·33 claims
- 2289US9812463B2Three-dimensional memory device containing vertically isolated charge storage regions and method of making thereofSANDISK TECHNOLOGIES LLC·Filed 2016·Granted Nov 7, 2017·6 cites·26 claims
- 2387US11342006B2Buried source line structure for boosting read schemeSANDISK TECHNOLOGIES LLC·Filed 2019·Granted May 24, 2022·3 cites·17 claims
- 2486US10692884B2Three-dimensional memory device including bottle-shaped memory stack structures and drain-select gate electrodes having cylindrical portionsSANDISK TECHNOLOGIES LLC·Filed 2018·Granted Jun 23, 2020·4 cites·14 claims
- 2584US6711060B2Non-volatile semiconductor memory and methods of driving, operating, and manufacturing this memoryRENESAS TECH CORP·Filed 2002·Granted Mar 23, 2004·30 cites·6 claims
- 2684US5191399ASolid-state imaging device with improved photodetectorMITSUBISHI ELECTRIC CORP·Filed 1991·Granted Mar 2, 1993·58 cites·2 claims
- 2783US10629611B2Three-dimensional memory device and methods of making the same using replacement drain select gate electrodesSANDISK TECHNOLOGIES LLC·Filed 2018·Granted Apr 21, 2020·2 cites·19 claims
- 2883US5877524ANon-volatile semiconductor memory deviceMITSUBISHI ELECTRIC CORP·Filed 1996·Granted Mar 2, 1999·52 cites·31 claims
- 2981US11456044B1Reverse VT-state operation and optimized BiCS device structureSANDISK TECHNOLOGIES LLC·Filed 2021·Granted Sep 27, 2022·1 cites·15 claims
- 3081US8084279B2Method of manufacturing semiconductor device that uses both a normal photomask and a phase shift mask for defining interconnect patternsKASAOKA TATSUO·Filed 2010·Granted Dec 27, 2011·8 cites·4 claims
- 3178US6566678B1Semiconductor device having a solid-state image sensorMITSUBISHI ELECTRIC CORP·Filed 2002·Granted May 20, 2003·22 cites·6 claims
- 3275US8575969B2Semiconductor device having differential pair transistors with a switchable tail currentSAKAKIBARA KIYOHIKO·Filed 2012·Granted Nov 5, 2013·5 cites·17 claims
- 3374US5238864AMethod of making solid-state imaging deviceMITSUBISHI ELECTRIC CORP·Filed 1992·Granted Aug 24, 1993·36 cites·4 claims
- 3470US5691560ANonvolatile semiconductor memory device and method of manufacturing the sameMITSUBISHI ELECTRIC CORP·Filed 1994·Granted Nov 25, 1997·25 cites·7 claims
- 3569US6466484B2Nonvolatile semiconductor memory device capable of suppressing reduction of bit line potential in write-back operation and erase methodMITSUBISHI ELECTRIC CORP·Filed 2002·Granted Oct 15, 2002·15 cites·8 claims
- 3668US11763907B2Reverse VT-state operation and optimized BiCS device structureSANDISK TECHNOLOGIES LLC·Filed 2022·Granted Sep 19, 2023·0 cites·20 claims
- 3767US6970385B2Non-volatile semiconductor memory device suppressing write-back faultRENESAS TECH CORP·Filed 2003·Granted Nov 29, 2005·15 cites·12 claims
- 3866US11227663B2Boosting read scheme with back-gate biasSANDISK TECHNOLOGIES LLC·Filed 2021·Granted Jan 18, 2022·0 cites·20 claims
- 3965US11004518B2Threshold voltage setting with boosting read schemeSANDISK TECHNOLOGIES LLC·Filed 2019·Granted May 11, 2021·1 cites·20 claims
- 4065US6667524B1Semiconductor device with a plurality of semiconductor elementsMITSUBISHI ELECTRIC CORP·Filed 2003·Granted Dec 23, 2003·12 cites·6 claims
- 4165US2022254382A1Buried source line structure for boosting read schemeSANDISK TECHNOLOGIES LLC·Filed 2022·Application pending·0 cites
- 4264US10957401B2Boosting read scheme with back-gate biasSANDISK TECHNOLOGIES LLC·Filed 2020·Granted Mar 23, 2021·0 cites·18 claims
- 4360US11631691B2Three-dimensional flat memory device including a dual dipole blocking dielectric layer and methods of making the sameSANDISK TECHNOLOGIES LLC·Filed 2020·Granted Apr 18, 2023·0 cites·7 claims
- 4460US11348649B2Threshold voltage setting with boosting read schemeSANDISK TECHNOLOGIES LLC·Filed 2020·Granted May 31, 2022·0 cites·20 claims
- 4560US6356480B1Nonvolatile semiconductor memory device capable of suppressing reduction of bit line potential in write-back operation and erase methodMITSUBISHI ELECTRIC CORP·Filed 2000·Granted Mar 12, 2002·11 cites·9 claims
- 4660US5621689ANonvolatile semiconductor memory device having controlled charge pump loadMITSUBISHI ELECTRIC CORP·Filed 1995·Granted Apr 15, 1997·19 cites·14 claims
- 4758US7358548B2Semiconductor integrated circuit having layout in which buffers or protection circuits are arranged in concentrated mannerRENESAS TECH CORP·Filed 2006·Granted Apr 15, 2008·1 cites·8 claims
- 4852US5189498ACharge coupled deviceMITSUBISHI ELECTRIC CORP·Filed 1990·Granted Feb 23, 1993·14 cites·5 claims
- 4951US10950311B2Boosting read scheme with back-gate biasSANDISK TECHNOLOGIES LLC·Filed 2019·Granted Mar 16, 2021·0 cites·11 claims
- 5050US7696081B2Method of manufacturing semiconductor device that uses both a normal photomask and a phase shift mask for defining interconnect patternsRENESAS TECH CORP·Filed 2008·Granted Apr 13, 2010·0 cites·14 claims
Showing the top 50 of 58 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →