Inventor · disambiguated record
Karl Brummel
Also filed as: BRUMMEL KARL · BRUMMEL KARL P
16 granted patents·3 pending applications·168 citations·filing 1996–2020
93Inventor score
Files withHEWLETT PACKARD DEVELOPMENT CO7INTEL CORP5HEWLETT PACKARD CO3SK HYNIX NAND PRODUCT SOLUTIONS CORP1
Top patents by PatentIndex Score
19 records- 0186US7409524B2System and method for responding to TLB missesHEWLETT PACKARD DEVELOPMENT CO·Filed 2005·Granted Aug 5, 2008·16 cites·20 claims
- 0283US11941458B2Maintaining storage namespace identifiers for live virtualized execution environment migrationSK HYNIX NAND PRODUCT SOLUTIONS CORP·Filed 2020·Granted Mar 26, 2024·2 cites·20 claims
- 0383US10505848B2Congestion management techniques for communication networksINTEL CORP·Filed 2015·Granted Dec 10, 2019·6 cites·25 claims
- 0476US7152192B2System and method of testing a plurality of memory blocks of an integrated circuit in parallelHEWLETT PACKARD DEVELOPMENT CO·Filed 2005·Granted Dec 19, 2006·11 cites·20 claims
- 0576US6625759B1Method and apparatus for verifying the fine-grained correctness of a behavioral model of a central processor unitHEWLETT PACKARD DEVELOPMENT CO·Filed 2000·Granted Sep 23, 2003·22 cites·18 claims
- 0673US7139936B2Method and apparatus for verifying the correctness of a processor behavioral modelHEWLETT PACKARD DEVELOPMENT CO·Filed 2003·Granted Nov 21, 2006·16 cites·18 claims
- 0772US6643800B1Method and apparatus for testing microarchitectural features by using tests written in microcodeHEWLETT PACKARD DEVELOPMENT CO·Filed 2000·Granted Nov 4, 2003·18 cites·6 claims
- 0868US10044626B2Reliable out-of order end-to-end protocol with robust window state overflow management and a multi-node system using sameINTEL CORP·Filed 2015·Granted Aug 7, 2018·2 cites·18 claims
- 0959US7543113B2Cache memory system and method capable of adaptively accommodating various memory line sizesHEWLETT PACKARD DEVELOPMENT CO·Filed 2004·Granted Jun 2, 2009·7 cites·15 claims
- 1058US5771241AMethod and apparatus for embedding operand synthesizing sequences in randomly generated testsHEWLETT PACKARD CO·Filed 1996·Granted Jun 23, 1998·21 cites·21 claims
- 1152US5784550AMethod for enhanced functional testing of a processor using dynamic trap handlersHEWLETT PACKARD CO·Filed 1996·Granted Jul 21, 1998·25 cites·20 claims
- 1246US6678853B1Method and apparatus for generating random codeHEWLETT PACKARD DEVELOPMENT CO·Filed 1999·Granted Jan 13, 2004·17 cites·21 claims
- 1344US11456972B2Methods and arrangements to accelerate array searchesINTEL CORP·Filed 2018·Granted Sep 27, 2022·0 cites·25 claims
- 1442US2004064267A1Method and apparatus for testing microarchitectural features by using tests written in microcodeFiled 2003·Application pending·0 cites
- 1541US11172016B2Device, method and system to enforce concurrency limits of a target node within a network fabricINTEL CORP·Filed 2017·Granted Nov 9, 2021·0 cites·25 claims
- 1641US2004078650A1Method and apparatus for testing errors in microprocessorsFiled 2002·Application pending·0 cites
- 1739US2004034820A1Apparatus and method for pseudorandom rare event injection to improve verification qualityFiled 2002·Application pending·0 cites
- 1833US10348634B2Technologies for tracking out-of-order network packetsINTEL CORP·Filed 2015·Granted Jul 9, 2019·0 cites·21 claims
- 1932US6564178B1Method and apparatus for evaluating processors for architectural complianceHEWLETT PACKARD CO·Filed 1999·Granted May 13, 2003·5 cites·31 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →