Inventor · disambiguated record
Eric Andrew Gouldey
Also filed as: GOULDEY ERIC · GOULDEY ERIC A · GOULDEY ERIC ANDREW
14 granted patents·7 pending applications·13 citations·filing 2012–2025
85Inventor score
Technology areasG06F
Top patents by PatentIndex Score
21 records- 0180US9170946B2Directory cache supporting non-atomic input/output operationsHUM HERBERT H·Filed 2012·Granted Oct 27, 2015·9 cites·16 claims
- 0275US12197335B2Canceling prefetch of cache blocks based on an address and a bit fieldSIFIVE INC·Filed 2023·Granted Jan 14, 2025·0 cites·20 claims
- 0374US12248401B2Eviction operations based on eviction message types of different prioritiesSIFIVE INC·Filed 2023·Granted Mar 11, 2025·0 cites·22 claims
- 0474US2025110896A1Downgrading a permission associated with data stored in a cacheSIFIVE INC·Filed 2024·Application pending·0 cites
- 0572US12259825B2Concurrent support for multiple cache inclusivity schemes using low priority evict operationsSIFIVE INC·Filed 2023·Granted Mar 25, 2025·0 cites·20 claims
- 0672US12204462B2Downgrading a permission associated with data stored in a cacheSIFIVE INC·Filed 2023·Granted Jan 21, 2025·0 cites·20 claims
- 0771US10866888B2Reservation architecture for overcommitted memoryINTEL CORP·Filed 2018·Granted Dec 15, 2020·1 cites·25 claims
- 0871US2025147761A1Canceling prefetch of cache blocks based on an address and a bit fieldSIFIVE INC·Filed 2025·Application pending·0 cites
- 0970US12306772B2Orderability of operationsSIFIVE INC·Filed 2023·Granted May 20, 2025·0 cites·20 claims
- 1069US12386764B2Selective transfer of data including a priority byteSIFIVE INC·Filed 2023·Granted Aug 12, 2025·0 cites·20 claims
- 1169US2025181507A1Eviction operations based on eviction message types of different prioritiesSIFIVE INC·Filed 2025·Application pending·0 cites
- 1268US2025173281A1Orderability of operationsSIFIVE INC·Filed 2025·Application pending·0 cites
- 1367US10248574B2Input/output translation lookaside buffer prefetchingINTEL CORP·Filed 2017·Granted Apr 2, 2019·1 cites·19 claims
- 1467US2025181519A1Concurrent support for multiple cache inclusivity schemes using low priority evict operationsSIFIVE INC·Filed 2025·Application pending·0 cites
- 1565US12332799B2Speculative request indicator in request messageSIFIVE INC·Filed 2023·Granted Jun 17, 2025·0 cites·21 claims
- 1665US12189544B2Transmitting a response with a request and state information about the requestSIFIVE INC·Filed 2023·Granted Jan 7, 2025·0 cites·20 claims
- 1764US11681611B2Reservation architecture for overcommitted memoryINTEL CORP·Filed 2020·Granted Jun 20, 2023·0 cites·25 claims
- 1859US9063855B2Fault handling at a transaction level by employing a token and a source-to-destination paradigm in a processor-based systemMCNAIRY CAMERON B·Filed 2013·Granted Jun 23, 2015·2 cites·25 claims
- 1958US12493551B2Cache coherency state request vector encoding and use thereofSIFIVE INC·Filed 2023·Granted Dec 9, 2025·0 cites·19 claims
- 2053US2024184663A1Variable Depth Pipeline for Error CorrectionSIFIVE INC·Filed 2023·Application pending·0 cites
- 2151US2024020012A1Memory Request Combination IndicationSIFIVE INC·Filed 2023·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →