Inventor · disambiguated record
Christopher M. Prindle
Also filed as: PRINDLE CHRISTOPHER · PRINDLE CHRISTOPHER M · PRINDLE CHRISTOPHER MICHAEL
20 granted patents·6 pending applications·206 citations·filing 2002–2019
94Inventor score
Files withGLOBALFOUNDRIES INC18ADVANCED MICRO DEVICES INC1BAARS PETER1FREESCALE SEMICONDUCTOR INC1GLOBAL FOUNDRIES INC1
Top patents by PatentIndex Score
26 records- 0198US10388770B1Gate and source/drain contact structures positioned above an active region of a transistor deviceGLOBALFOUNDRIES INC·Filed 2018·Granted Aug 20, 2019·36 cites·18 claims
- 0297US9147748B1Methods of forming replacement spacer structures on semiconductor devicesGLOBALFOUNDRIES INC·Filed 2014·Granted Sep 29, 2015·36 cites·14 claims
- 0396US10388747B1Gate contact structure positioned above an active region with air gaps positioned adjacent the gate structureGLOBALFOUNDRIES INC·Filed 2018·Granted Aug 20, 2019·21 cites·20 claims
- 0495US9640533B2Methods, apparatus and system for providing source-drain epitaxy layer with lateral over-growth suppressionGLOBALFOUNDRIES INC·Filed 2015·Granted May 2, 2017·14 cites·8 claims
- 0594US9806078B1FinFET spacer formation on gate sidewalls, between the channel and source/drain regionsGLOBALFOUNDRIES INC·Filed 2016·Granted Oct 31, 2017·9 cites·17 claims
- 0691US9236452B2Raised source/drain EPI with suppressed lateral EPI overgrowthGLOBALFOUNDRIES INC·Filed 2014·Granted Jan 12, 2016·10 cites·15 claims
- 0789US9876077B1Methods of forming a protection layer on an isolation region of IC products comprising FinFET devicesGLOBALFOUNDRIES INC·Filed 2016·Granted Jan 23, 2018·5 cites·17 claims
- 0888US10699965B1Removal of epitaxy defects in transistorsIBM·Filed 2019·Granted Jun 30, 2020·4 cites·20 claims
- 0986US9184263B2Methods of forming gate structures for semiconductor devices using a replacement gate technique and the resulting devicesGLOBALFOUNDRIES INC·Filed 2013·Granted Nov 10, 2015·7 cites·20 claims
- 1085US7601641B1Two step optical planarizing layer etchGLOBAL FOUNDRIES INC·Filed 2008·Granted Oct 13, 2009·10 cites·18 claims
- 1185US6924232B2Semiconductor process and composition for forming a barrier material overlying copperFREESCALE SEMICONDUCTOR INC·Filed 2003·Granted Aug 2, 2005·36 cites·20 claims
- 1279US9496354B2Semiconductor devices with dummy gate structures partially on isolation regionsGLOBALFOUNDRIES INC·Filed 2015·Granted Nov 15, 2016·2 cites·18 claims
- 1378US10734525B2Gate-all-around transistor with spacer support and methods of forming sameGLOBALFOUNDRIES INC·Filed 2018·Granted Aug 4, 2020·2 cites·14 claims
- 1478US8735236B2High-k metal gate electrode structure formed by removing a work function on sidewalls in replacement gate technologyHEMPEL KLAUS·Filed 2011·Granted May 27, 2014·5 cites·17 claims
- 1576US8748302B2Replacement gate approach for high-k metal gate stacks by using a multi-layer contact levelPRINDLE CHRISTOPHER M·Filed 2012·Granted Jun 10, 2014·6 cites·9 claims
- 1673US10170544B2Integrated circuit products that include FinFET devices and a protection layer formed on an isolation regionGLOBALFOUNDRIES INC·Filed 2017·Granted Jan 1, 2019·1 cites·20 claims
- 1767US9230802B2Transistor(s) with different source/drain channel junction characteristics, and methods of fabricationGLOBALFOUNDRIES INC·Filed 2014·Granted Jan 5, 2016·2 cites·20 claims
- 1854US10068978B2Methods, apparatus and system for providing source-drain epitaxy layer with lateral over-growth suppressionGLOBALFOUNDRIES INC·Filed 2017·Granted Sep 4, 2018·0 cites·6 claims
- 1948US2016056238A1Raised source/drain epi with suppressed lateral epi overgrowthGLOBALFOUNDRIES INC·Filed 2015·Application pending·0 cites
- 2045US2010072623A1Semiconductor device with improved contact plugs, and related fabrication methodsADVANCED MICRO DEVICES INC·Filed 2008·Application pending·0 cites
- 2144US9685384B1Devices and methods of forming epi for aggressive gate pitchGLOBALFOUNDRIES INC·Filed 2016·Granted Jun 20, 2017·0 cites·13 claims
- 2243US2015340468A1Recessed channel fin device with raised source and drain regionsGLOBALFOUNDRIES INC·Filed 2014·Application pending·0 cites
- 2341US10290738B2Methods of forming epi semiconductor material on a recessed fin in the source/drain regions of a FinFET deviceGLOBALFOUNDRIES INC·Filed 2017·Granted May 14, 2019·0 cites·18 claims
- 2438US2019081145A1Contact to source/drain regions and method of forming sameGLOBALFOUNDRIES INC·Filed 2017·Application pending·0 cites
- 2537US2013049123A1Semiconductor Device with DRAM Word Lines and Gate Electrodes in Non-Memory Regions of the Device Comprised of a Metal, and Methods of Making SameBAARS PETER·Filed 2011·Application pending·0 cites
- 2634US2003203615A1Method for depositing barrier layers in an openingFiled 2002·Application pending·0 cites
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