Inventor · disambiguated record
Salma Ayub
Also filed as: AYUB SALMA
26 granted patents·2 pending applications·35 citations·filing 2015–2023
93Inventor score
Technology areasG06F
Files withIBM28
Top patents by PatentIndex Score
28 records- 0198US11144319B1Redistribution of architected states for a processor register fileIBM·Filed 2020·Granted Oct 12, 2021·19 cites·20 claims
- 0289US11941398B1Fast mapper restore for flush in processorIBM·Filed 2022·Granted Mar 26, 2024·1 cites·20 claims
- 0387US9740620B2Distributed history buffer flush and restore handling in a parallel slice designIBM·Filed 2015·Granted Aug 22, 2017·5 cites·13 claims
- 0483US11531548B1Fast perfect issue of dependent instructions in a distributed issue queue systemIBM·Filed 2021·Granted Dec 20, 2022·1 cites·20 claims
- 0582US9747217B2Distributed history buffer flush and restore handling in a parallel slice designIBM·Filed 2015·Granted Aug 29, 2017·3 cites·7 claims
- 0681US10133576B2Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entriesIBM·Filed 2015·Granted Nov 20, 2018·2 cites·18 claims
- 0780US12061909B2Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entriesIBM·Filed 2023·Granted Aug 13, 2024·0 cites·21 claims
- 0880US10949213B2Logical register recovery within a processorIBM·Filed 2018·Granted Mar 16, 2021·2 cites·20 claims
- 0974US11734010B2Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entriesIBM·Filed 2021·Granted Aug 22, 2023·0 cites·21 claims
- 1073US10120693B2Fast multi-width instruction issue in parallel slice processorIBM·Filed 2018·Granted Nov 6, 2018·1 cites·20 claims
- 1165US10255071B2Method and apparatus for managing a speculative transaction in a processing unitIBM·Filed 2015·Granted Apr 9, 2019·1 cites·20 claims
- 1264US11360779B2Logical register recovery within a processorIBM·Filed 2020·Granted Jun 14, 2022·0 cites·20 claims
- 1364US11150907B2Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entriesIBM·Filed 2018·Granted Oct 19, 2021·0 cites·19 claims
- 1461US10942745B2Fast multi-width instruction issue in parallel slice processorIBM·Filed 2018·Granted Mar 9, 2021·0 cites·18 claims
- 1556US2016202988A1Parallel slice processing method using a recirculating load-store queue for fast deallocation of issue queue entriesIBM·Filed 2015·Application pending·0 cites
- 1655US9996359B2Fast multi-width instruction issue in parallel slice processorIBM·Filed 2016·Granted Jun 12, 2018·0 cites·20 claims
- 1753US10248421B2Operation of a multi-slice processor with reduced flush and restore latencyIBM·Filed 2016·Granted Apr 2, 2019·0 cites·6 claims
- 1853US10241790B2Operation of a multi-slice processor with reduced flush and restore latencyIBM·Filed 2015·Granted Mar 26, 2019·0 cites·12 claims
- 1952US12204902B2Routing instruction results to a register block of a subdivided register file based on register block utilization rateIBM·Filed 2021·Granted Jan 21, 2025·0 cites·15 claims
- 2050US11068267B2High bandwidth logical register flush recoveryIBM·Filed 2019·Granted Jul 20, 2021·0 cites·20 claims
- 2149US11561794B2Evicting and restoring information using a single port of a logical register mapper and history buffer in a microprocessor comprising multiple main register file entries mapped to one accumulator register file entryIBM·Filed 2021·Granted Jan 24, 2023·0 cites·20 claims
- 2249US10649779B2Variable latency pipe for interleaving instruction tags in a microprocessorIBM·Filed 2016·Granted May 12, 2020·0 cites·7 claims
- 2348US11188332B2System and handling of register data in processorsIBM·Filed 2019·Granted Nov 30, 2021·0 cites·17 claims
- 2447US10613868B2Variable latency pipe for interleaving instruction tags in a microprocessorIBM·Filed 2015·Granted Apr 7, 2020·0 cites·11 claims
- 2545US10831492B2Most favored branch issueIBM·Filed 2018·Granted Nov 10, 2020·0 cites·6 claims
- 2643US10740107B2Operation of a multi-slice processor implementing load-hit-store handlingIBM·Filed 2016·Granted Aug 11, 2020·0 cites·17 claims
- 2743US10445100B2Broadcasting messages between execution slices for issued instructions indicating when execution results are readyIBM·Filed 2016·Granted Oct 15, 2019·0 cites·17 claims
- 2839US2017364356A1Techniques for implementing store instructions in a multi-slice processor architectureIBM·Filed 2016·Application pending·0 cites
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →