Inventor · disambiguated record
Thomas J. Shepherd
Also filed as: SHEPHERD THOMAS J · SHEPHERD THOMAS JOSEPH
7 granted patents·2 pending applications·38 citations·filing 2004–2021
80Inventor score
Top patents by PatentIndex Score
9 records- 0193US10275306B1System and method for memory control having adaptively split addressing of error-protected data words in memory transactions for inline storage configurationsCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Apr 30, 2019·14 cites·20 claims
- 0292US10769013B1Caching error checking data for memory having inline storage configurationsCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted Sep 8, 2020·17 cites·20 claims
- 0385US10642684B1Memory command interleavingCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted May 5, 2020·5 cites·20 claims
- 0456US11663149B1System and method for memory managementCADENCE DESIGN SYSTEMS INC·Filed 2021·Granted May 30, 2023·0 cites·20 claims
- 0551US8643523B1Sharing embedded ADC resources across hardware and software sample-conversion queues with improved availability of the resourcesSHEPHERD THOMAS J·Filed 2012·Granted Feb 4, 2014·2 cites·20 claims
- 0645US7460135B2Two dimensional rotation of sub-sampled color space imagesTEXAS INSTRUMENTS INC·Filed 2006·Granted Dec 2, 2008·0 cites·20 claims
- 0742US7280116B2Pixel data preprocessing methods and systemsTEXAS INSTRUMENTS INC·Filed 2005·Granted Oct 9, 2007·0 cites·7 claims
- 0833US2006022985A1Preemptive rendering arbitration between processor hosts and display controllersTEXAS INSTRUMENTS INC·Filed 2004·Application pending·0 cites
- 0928US2006026530A1DMA overlay addressing methodology for optimizing power and improving memory bandwidth for display enginesTEXAS INSTRUMENTS INC·Filed 2004·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →