Inventor · disambiguated record
Glenn E. Starnes
Also filed as: STARNES GLENN · STARNES GLENN E
10 granted patents·158 citations·filing 1995–2022
88Inventor score
Top patents by PatentIndex Score
10 records- 0190US12130654B2Area-efficient scalable memory read-data multiplexing and latchingINTEL CORP·Filed 2022·Granted Oct 29, 2024·2 cites·23 claims
- 0288US6157583AIntegrated circuit memory having a fuse detect circuit and method thereforMOTOROLA INC·Filed 1999·Granted Dec 5, 2000·72 cites·20 claims
- 0379US7746716B2Memory having a dummy bitline for timing controlFREESCALE SEMICONDUCTOR INC·Filed 2007·Granted Jun 29, 2010·13 cites·20 claims
- 0476US5554942AIntegrated circuit memory having a power supply independent input bufferMOTOROLA INC·Filed 1995·Granted Sep 10, 1996·42 cites·16 claims
- 0574US7518947B2Self-timed memory having common timing control circuit and method thereforFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted Apr 14, 2009·10 cites·19 claims
- 0665US11619963B2Area-efficient scalable memory read-data multiplexing and latchingINTEL CORP·Filed 2021·Granted Apr 4, 2023·0 cites·19 claims
- 0755US6108266AMemory utilizing a programmable delay to control address buffersMOTOROLA INC·Filed 1999·Granted Aug 22, 2000·16 cites·4 claims
- 0852US9263100B2Bypass system and method that mimics clock to data memory read timingFREESCALE SEMICONDUCTOR INC·Filed 2013·Granted Feb 16, 2016·1 cites·20 claims
- 0949US7397722B1Multiple block memory with complementary data pathFREESCALE SEMICONDUCTOR INC·Filed 2007·Granted Jul 8, 2008·2 cites·20 claims
- 1048US11029720B2Area-efficient scalable memory read-data multiplexing and latchingINTEL CORP·Filed 2019·Granted Jun 8, 2021·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →