Inventor · disambiguated record
Stephen Gualandri
Also filed as: GUALANDRI STEPHEN · GUALANDRI STEPHEN J
12 granted patents·1 pending application·139 citations·filing 2000–2012
91Inventor score
Top patents by PatentIndex Score
13 records- 0189US6438032B1Non-volatile memory with peak current noise reductionMICRON TECHNOLOGY INC·Filed 2001·Granted Aug 20, 2002·50 cites·43 claims
- 0283US7864607B2Negative voltage discharge scheme to improve snapback in a non-volatile memoryMICRON TECHNOLOGY INC·Filed 2007·Granted Jan 4, 2011·13 cites·22 claims
- 0378US6714458B2High voltage positive and negative two-phase discharge system and method for channel erase in flash memory devicesMICRON TECHNOLOGY INC·Filed 2002·Granted Mar 30, 2004·19 cites·42 claims
- 0476US7248521B2Negative voltage discharge scheme to improve snapback in a non-volatile memoryMICRON TECHNOLOGY INC·Filed 2005·Granted Jul 24, 2007·9 cites·36 claims
- 0568US7200047B2High voltage positive and negative two-phase discharge system and method for channel erase in flash memory devicesMICRON TECHNOLOGY INC·Filed 2005·Granted Apr 3, 2007·5 cites·20 claims
- 0666US6791893B2Regulating voltages in semiconductor devicesMICRON TECHNOLOGY INC·Filed 2002·Granted Sep 14, 2004·11 cites·21 claims
- 0762US6937517B2Clock regulation scheme for varying loadsMICRON TECHNOLOGY INC·Filed 2002·Granted Aug 30, 2005·16 cites·28 claims
- 0856US6477082B2Burst access memory with zero wait statesMICRON TECHNOLOGY INC·Filed 2000·Granted Nov 5, 2002·9 cites·80 claims
- 0949US6868016B2High voltage positive and negative two-phase discharge system and method for channel erase in flash memory devicesMICRON TECHNOLOGY INC·Filed 2004·Granted Mar 15, 2005·4 cites·24 claims
- 1042US7352643B2Regulating voltages for refresh operation using flash trim bits in semiconductor memory devicesMICRON TECHNOLOGY INC·Filed 2007·Granted Apr 1, 2008·0 cites·11 claims
- 1142US7173869B2Regulating voltages in semiconductor devicesMICRON TECHNOLOGY INC·Filed 2004·Granted Feb 6, 2007·2 cites·18 claims
- 1242US2012294085A1Multi-partition architecture for memoryPEKNY THEODORE T·Filed 2012·Application pending·0 cites
- 1338US8233322B2Multi-partition memory with separated read and algorithm datalinesPEKNY THEODORE T·Filed 2003·Granted Jul 31, 2012·1 cites·25 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →