Inventor · disambiguated record
Philip John Cacharelis
Also filed as: CACHARELIS PHILIP J · CACHARELIS PHILIP JOHN
10 granted patents·727 citations·filing 1990–2005
93Inventor score
Top patents by PatentIndex Score
10 records- 0196US5889315ASemiconductor structure having two levels of buried regionsNAT SEMICONDUCTOR CORP·Filed 1995·Granted Mar 30, 1999·231 cites·114 claims
- 0295US5899714AFabrication of semiconductor structure having two levels of buried regionsNAT SEMICONDUCTOR CORP·Filed 1995·Granted May 4, 1999·207 cites·57 claims
- 0385US5108939AMethod of making a non-volatile memory cell utilizing polycrystalline silicon spacer tunnel regionNAT SEMICONDUCTOR CORP·Filed 1990·Granted Apr 28, 1992·68 cites·13 claims
- 0482US5550072AMethod of fabrication of integrated circuit chip containing EEPROM and capacitorNAT SEMICONDUCTOR CORP·Filed 1994·Granted Aug 27, 1996·48 cites·16 claims
- 0579US6313901B1Liquid crystal display fabrication process using a final rapid thermal annealNAT SEMICONDUCTOR CORP·Filed 1999·Granted Nov 6, 2001·61 cites·8 claims
- 0676US5591658AMethod of fabricating integrated circuit chip containing EEPROM and capacitorNAT SEMICONDUCTOR CORP·Filed 1995·Granted Jan 7, 1997·32 cites·4 claims
- 0772US7102188B1High reliability electrically erasable and programmable read-only memory (EEPROM)AMI SEMICONDUCTOR INC·Filed 2005·Granted Sep 5, 2006·6 cites·41 claims
- 0872US5894147AMemory transistor having underlapped floating gateNAT SEMICONDUCTOR CORP·Filed 1995·Granted Apr 13, 1999·26 cites·2 claims
- 0964US6437839B1Liquid crystal on silicon (LCOS) display pixel with multiple storage capacitorsNAT SEMICONDUCTOR COMPANY·Filed 1999·Granted Aug 20, 2002·37 cites·22 claims
- 1042US6373543B1Process for forming silicon LC pixel cell having planar alignment layers of uniform thicknessNAT SEMICONDUCTOR CORP·Filed 1999·Granted Apr 16, 2002·11 cites·10 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →