Inventor · disambiguated record
Erik Geiss
Also filed as: GEISS ERIK · GEISS ERIK P
10 granted patents·1 pending application·96 citations·filing 2008–2018
88Inventor score
Top patents by PatentIndex Score
11 records- 0195US8557666B2Methods for fabricating integrated circuitsWEI ANDY C·Filed 2011·Granted Oct 15, 2013·32 cites·18 claims
- 0289US9397004B2Methods for fabricating FinFET integrated circuits with simultaneous formation of local contact openingsGLOBALFOUNDRIES INC·Filed 2014·Granted Jul 19, 2016·10 cites·14 claims
- 0387US8927407B2Method of forming self-aligned contacts for a semiconductor deviceBAARS PETER·Filed 2012·Granted Jan 6, 2015·9 cites·19 claims
- 0486US8071485B2Method of semiconductor manufacturing for small featuresLEE DOUG H·Filed 2009·Granted Dec 6, 2011·17 cites·19 claims
- 0585US9136175B2Methods for fabricating integrated circuitsGLOBALFOUNDRIES INC·Filed 2013·Granted Sep 15, 2015·6 cites·20 claims
- 0685US7601641B1Two step optical planarizing layer etchGLOBAL FOUNDRIES INC·Filed 2008·Granted Oct 13, 2009·10 cites·18 claims
- 0784US8614123B2Method of forming a semiconductor device by using sacrificial gate electrodes and sacrificial self-aligned contact structuresWEI ANDY·Filed 2011·Granted Dec 24, 2013·7 cites·20 claims
- 0879US10707175B2Asymmetric overlay mark for overlay measurementGLOBALFOUNDRIES INC·Filed 2018·Granted Jul 7, 2020·3 cites·19 claims
- 0977US10475890B2Scaled memory structures or other logic devices with middle of the line cutsGLOBALFOUNDRIES INC·Filed 2017·Granted Nov 12, 2019·2 cites·14 claims
- 1038US2013193489A1Integrated circuits including copper local interconnects and methods for the manufacture thereofBAARS PETER·Filed 2012·Application pending·0 cites
- 1133US8592302B2Patterning method for fabrication of a semiconductor deviceGEISS ERIK P·Filed 2011·Granted Nov 26, 2013·0 cites·10 claims
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