Inventor · disambiguated record
Tiberiu Chelcea
Also filed as: CHELCEA TIBERIU
2 granted patents·1 pending application·77 citations·filing 2001–2001
66Inventor score
Technology areasG06F
Top patents by PatentIndex Score
3 records- 0184US6850092B2Low latency FIFO circuits for mixed asynchronous and synchronous systemsUNIV COLUMBIA·Filed 2001·Granted Feb 1, 2005·57 cites·42 claims
- 0266US7197582B2Low latency FIFO circuit for mixed clock systemsCHELCEA TIBERIU·Filed 2001·Granted Mar 27, 2007·20 cites·11 claims
- 0336US2004128413A1Low latency fifo circuits for mixed asynchronous and synchronous systemsFiled 2001·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →