Inventor · disambiguated record
Suresh Yeruva
Also filed as: YERUVA SURESH · YERUVA SURESH B · YERUVA SURESH BABU
6 granted patents·3 pending applications·14 citations·filing 2006–2024
75Inventor score
Technology areasH10W
Top patents by PatentIndex Score
9 records- 0186US11081460B2Methods and systems for manufacturing pillar structures on semiconductor devicesMICRON TECHNOLOGY INC·Filed 2018·Granted Aug 3, 2021·5 cites·22 claims
- 0280US8952532B2Integrated circuit package with spatially varied solder resist opening dimensionZHENG TIEYU·Filed 2013·Granted Feb 10, 2015·7 cites·18 claims
- 0371US2024297134A1Electronic packageSKYWORKS SOLUTIONS INC·Filed 2024·Application pending·0 cites
- 0471US2024297130A1Method for manufacturing an electronic packageSKYWORKS SOLUTIONS INC·Filed 2024·Application pending·0 cites
- 0567US9312237B2Integrated circuit package with spatially varied solder resist opening dimensionINTEL CORP·Filed 2014·Granted Apr 12, 2016·2 cites·6 claims
- 0664US11735549B2Methods and systems for manufacturing pillar structures on semiconductor devicesMICRON TECHNOLOGY INC·Filed 2021·Granted Aug 22, 2023·0 cites·18 claims
- 0758US10784224B2Semiconductor devices with underfill control features, and associated systems and methodsMICRON TECHNOLOGY INC·Filed 2019·Granted Sep 22, 2020·0 cites·18 claims
- 0849US10424553B2Semiconductor devices with underfill control features, and associated systems and methodsMICRON TECHNOLOGY INC·Filed 2016·Granted Sep 24, 2019·0 cites·24 claims
- 0935US2008093723A1Passive placement in wire-bonded microelectronicsMYERS TODD B·Filed 2006·Application pending·0 cites
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →