Inventor · disambiguated record
Brian E. Curcio
Also filed as: CURCIO BRIAN E · CURCIO BRIAN EUGENE
21 granted patents·1 pending application·418 citations·filing 2001–2013
96Inventor score
Files withIBM16CURCIO BRIAN E2HEWLETT PACKARD DEVELOPMENT CO2BLAIR DUSTIN W1HEWLETT PACKARD DEVELOPMENT CO LP1
Top patents by PatentIndex Score
22 records- 0197US6465084B1Method and structure for producing Z-axis interconnection assembly of printed wiring board elementsIBM·Filed 2001·Granted Oct 15, 2002·116 cites·12 claims
- 0294US6452117B2Method for filling high aspect ratio via holes in electronic substrates and the resulting holesIBM·Filed 2001·Granted Sep 17, 2002·76 cites·13 claims
- 0391US6638607B1Method and structure for producing Z-axis interconnection assembly of printed wiring board elementsIBM·Filed 2002·Granted Oct 28, 2003·40 cites·9 claims
- 0489US8474934B1Method for improving gloss of a printCURCIO BRIAN E·Filed 2010·Granted Jul 2, 2013·10 cites·14 claims
- 0587US6581280B2Method for filling high aspect ratio via holes in electronic substratesIBM·Filed 2002·Granted Jun 24, 2003·40 cites·18 claims
- 0687US6504111B2Solid via layer to layer interconnectIBM·Filed 2001·Granted Jan 7, 2003·29 cites·16 claims
- 0786US6645607B2Method and structure for producing Z-axis interconnection assembly of printed wiring board elementsIBM·Filed 2002·Granted Nov 11, 2003·24 cites·14 claims
- 0880US8596746B2Inkjet pen/printhead with shipping fluidCURCIO BRIAN E·Filed 2009·Granted Dec 3, 2013·8 cites·15 claims
- 0977US6570102B2Structure for high speed printed wiring boards with multiple differential impedance-controlled layerIBM·Filed 2001·Granted May 27, 2003·26 cites·20 claims
- 1074US8267498B1Methods, apparatus and articles of manufacture to control gloss qualityBLAIR DUSTIN W·Filed 2010·Granted Sep 18, 2012·3 cites·15 claims
- 1170US9798259B2Electrostatic ink compositions, methods and print substratesHEWLETT PACKARD DEVELOPMENT CO LP·Filed 2013·Granted Oct 24, 2017·1 cites·13 claims
- 1270US7303639B2Method for producing Z-axis interconnection assembly of printed wiring board elementsIBM·Filed 2005·Granted Dec 4, 2007·3 cites·4 claims
- 1367US7076869B2Solid via layer to layer interconnectIBM·Filed 2002·Granted Jul 18, 2006·10 cites·20 claims
- 1460US7914110B2Purging fluid from fluid-ejection nozzles by performing spit-wipe operationsHEWLETT PACKARD DEVELOPMENT CO·Filed 2007·Granted Mar 29, 2011·2 cites·20 claims
- 1560US6969436B2Method and structure for producing Z-axis interconnection assembly of printed wiring board elementsIBM·Filed 2003·Granted Nov 29, 2005·6 cites·18 claims
- 1660US6790305B2Method and structure for small pitch z-axis electrical interconnectionsIBM·Filed 2002·Granted Sep 14, 2004·8 cites·9 claims
- 1759US6634543B2Method of forming metallic z-interconnects for laminate chip packages and boardsIBM·Filed 2002·Granted Oct 21, 2003·7 cites·17 claims
- 1855US7402254B2Method and structure for producing Z-axis interconnection assembly of printed wiring board elementsIBM·Filed 2003·Granted Jul 22, 2008·4 cites·18 claims
- 1955US6955849B2Method and structure for small pitch z-axis electrical interconnectionsIBM·Filed 2004·Granted Oct 18, 2005·5 cites·9 claims
- 2044US8356878B2Method of printing imagesHEWLETT PACKARD DEVELOPMENT CO·Filed 2011·Granted Jan 22, 2013·0 cites·20 claims
- 2141US6776852B2Process of removing holefill residue from a metallic surface of an electronic substrateIBM·Filed 2002·Granted Aug 17, 2004·0 cites·15 claims
- 2238US2003041966A1Method of joining laminates for z-axis interconnectionIBM·Filed 2001·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →