Inventor · disambiguated record
Serge Lasserre
Also filed as: LASSERRE SERGE · LASSERRE SERGE B · LASSERRE SERGE BERNARD
51 granted patents·9 pending applications·1,311 citations·filing 1997–2024
99Inventor score
Top patents by PatentIndex Score
60 records- 0194US6369855B1Audio and video decoder circuit and systemTEXAS INSTRUMENTS INC·Filed 1997·Granted Apr 9, 2002·335 cites·12 claims
- 0290US6751706B2Multiple microprocessors with a shared cacheTEXAS INSTRUMENTS INC·Filed 2001·Granted Jun 15, 2004·65 cites·13 claims
- 0389US6681297B2Software controlled cache configuration based on average miss rateTEXAS INSTRUMENTS INC·Filed 2001·Granted Jan 20, 2004·55 cites·13 claims
- 0486US7509391B1Unified memory management system for multi processor heterogeneous architectureTEXAS INSTRUMENTS INC·Filed 1999·Granted Mar 24, 2009·119 cites·17 claims
- 0586US6789172B2Cache and DMA with a global valid bitTEXAS INSTRUMENTS INC·Filed 2001·Granted Sep 7, 2004·48 cites·8 claims
- 0685US6826652B1Smart cacheTEXAS INSTRUMENTS INC·Filed 2000·Granted Nov 30, 2004·41 cites·15 claims
- 0784US6742104B2Master/slave processing system with shared translation lookaside bufferTEXAS INSTRUMENTS INC·Filed 2001·Granted May 25, 2004·42 cites·28 claims
- 0884US6310657B1Real time window address calculation for on-screen displayTEXAS INSTRUMENTS INC·Filed 2000·Granted Oct 30, 2001·35 cites·14 claims
- 0983US6697916B2Cache with block prefetch and DMATEXAS INSTRUMENTS INC·Filed 2001·Granted Feb 24, 2004·36 cites·12 claims
- 1081US6684280B2Task based priority arbitrationTEXAS INSTRUMENTS INC·Filed 2001·Granted Jan 27, 2004·29 cites·20 claims
- 1179US6745293B2Level 2 smartcache architecture supporting simultaneous multiprocessor accessesTEXAS INSTRUMENTS INC·Filed 2001·Granted Jun 1, 2004·27 cites·10 claims
- 1279US6226291B1Transport stream packet parser systemTEXAS INSTRUMENTS INC·Filed 1997·Granted May 1, 2001·70 cites·11 claims
- 1378US6760829B2MMU descriptor having big/little endian bit to control the transfer data between devicesTEXAS INSTRUMENTS INC·Filed 2001·Granted Jul 6, 2004·24 cites·11 claims
- 1477US9141561B2Master circuits having dynamic priority leads coupled with memory controllerTEXAS INSTRUMENTS INC·Filed 2012·Granted Sep 22, 2015·5 cites·4 claims
- 1577US6851072B2Fault management and recovery based on task-IDTEXAS INSTRUMENTS INC·Filed 2001·Granted Feb 1, 2005·22 cites·13 claims
- 1676US6772326B2Interruptible and re-entrant cache clean range instructionTEXAS INSTRUMENTS INC·Filed 2002·Granted Aug 3, 2004·22 cites·19 claims
- 1776US6754781B2Cache with DMA and dirty bitsTEXAS INSTRUMENTS INC·Filed 2001·Granted Jun 22, 2004·22 cites·19 claims
- 1875US7360060B2Using IMPDEP2 for system commands related to Java accelerator hardwareTEXAS INSTRUMENTS INC·Filed 2003·Granted Apr 15, 2008·19 cites·21 claims
- 1974US6792508B1Cache with multiple fill modesTEXAS INSTRUMENTS INC·Filed 2000·Granted Sep 14, 2004·19 cites·24 claims
- 2074US6678797B2Cache/smartcache with interruptible block prefetchTEXAS INSTRUMENTS INC·Filed 2001·Granted Jan 13, 2004·19 cites·10 claims
- 2172US6412048B1Traffic controller using priority and burst control for reducing access latencyTEXAS INSTRUMENTS INC·Filed 1998·Granted Jun 25, 2002·47 cites·13 claims
- 2271US7434029B2Inter-processor controlTEXAS INSTRUMENTS INC·Filed 2003·Granted Oct 7, 2008·13 cites·22 claims
- 2369US6253297B1Memory control using memory state information for reducing access latencyTEXAS INSTRUMENTS INC·Filed 1998·Granted Jun 26, 2001·43 cites·24 claims
- 2468US6742103B2Processing system with shared translation lookaside bufferTEXAS INSTRUMENTS INC·Filed 2001·Granted May 25, 2004·13 cites·34 claims
- 2567US7712098B2Data transfer controlled by task attributesTEXAS INSTRUMENTS INC·Filed 2002·Granted May 4, 2010·13 cites·15 claims
- 2666US6728838B2Cache operation based on range of addressesTEXAS INSTRUMENTS INC·Filed 2001·Granted Apr 27, 2004·11 cites·13 claims
- 2764US8032891B2Energy-aware scheduling of application executionTEXAS INSTRUMENTS INC·Filed 2002·Granted Oct 4, 2011·14 cites·20 claims
- 2864US7434021B2Memory allocation in a multi-processor systemTEXAS INSTRUMENTS INC·Filed 2004·Granted Oct 7, 2008·10 cites·16 claims
- 2964US6934820B2Traffic controller using priority and burst control for reducing access latencyTEXAS INSTRUMENTS INC·Filed 2002·Granted Aug 23, 2005·7 cites·20 claims
- 3062US8539159B2Dirty cache line write back policy based on stack size trend informationCHAUVEL GERARD·Filed 2003·Granted Sep 17, 2013·8 cites·4 claims
- 3160US7941790B2Data processing apparatus, system and methodTEXAS INSTRUMENTS INC·Filed 2001·Granted May 10, 2011·9 cites·22 claims
- 3259US8190861B2Micro-sequence based security modelCHAUVEL GERARD·Filed 2007·Granted May 29, 2012·1 cites·26 claims
- 3359US7634643B2Stack register reference control bit in source operand of instructionTEXAS INSTRUMENTS INC·Filed 2003·Granted Dec 15, 2009·6 cites·14 claims
- 3458US7330937B2Management of stack-based memory usage in a processorTEXAS INSTRUMENTS INC·Filed 2004·Granted Feb 12, 2008·6 cites·34 claims
- 3556US7162586B2Synchronizing stack storageTEXAS INSTRUMENTS INC·Filed 2003·Granted Jan 9, 2007·4 cites·13 claims
- 3655US7496930B2Accessing device driver memory in programming language representationTEXAS INSTRUMENTS INC·Filed 2004·Granted Feb 24, 2009·4 cites·26 claims
- 3755US6968400B2Local memory with indicator bits to support concurrent DMA and CPU accessTEXAS INSTRUMENTS INC·Filed 2001·Granted Nov 22, 2005·4 cites·16 claims
- 3855US2025363248A1Data encryption for data transfers between semiconductor dies using a keystream generatorQUALCOMM INC·Filed 2024·Application pending·0 cites
- 3953US7565385B2Embedded garbage collectionTEXAS INSTRUMENTS INC·Filed 2004·Granted Jul 21, 2009·3 cites·11 claims
- 4052US7058765B2Processor with a split stackTEXAS INSTRUMENTS INC·Filed 2003·Granted Jun 6, 2006·2 cites·20 claims
- 4152US6996683B2Cache coherency in a multi-processor systemTEXAS INSTRUMENTS INC·Filed 2003·Granted Feb 7, 2006·2 cites·13 claims
- 4248US6766421B2Fast hardware looping mechanism for cache cleaning and flushing of cache entries corresponding to a qualifier fieldTEXAS INSTRUMENTS INC·Filed 2001·Granted Jul 20, 2004·2 cites·27 claims
- 4347US7386671B2Smart cacheTEXAS INSTRUMENTS INC·Filed 2004·Granted Jun 10, 2008·0 cites·11 claims
- 4445US7840784B2Test and skip processor instruction having at least one register operandTEXAS INSTRUMENTS INC·Filed 2003·Granted Nov 23, 2010·0 cites·25 claims
- 4545US7840782B2Mixed stack-based RISC processorTEXAS INSTRUMENTS INC·Filed 2003·Granted Nov 23, 2010·0 cites·38 claims
- 4645US7555611B2Memory management of local variables upon a change of contextTEXAS INSTRUMENTS INC·Filed 2003·Granted Jun 30, 2009·1 cites·22 claims
- 4744US8429383B2Multi-processor computing system having a JAVA stack machine and a RISC-based processorCHAUVEL GERARD·Filed 2003·Granted Apr 23, 2013·0 cites·14 claims
- 4844US7757067B2Pre-decoding bytecode prefixes selectively incrementing stack machine program counterTEXAS INSTRUMENTS INC·Filed 2003·Granted Jul 13, 2010·0 cites·6 claims
- 4944US2004024969A1Methods and apparatuses for managing memoryTEXAS INSTRUMENTS INC·Filed 2003·Application pending·0 cites
- 5044US2004024999A1Micro-sequence execution in a processorTEXAS INSTRUMENTS INC·Filed 2003·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →