Inventor · disambiguated record
Ramesh Senthinathan
Also filed as: SENTHINATHAN RAMESH
16 granted patents·4 pending applications·138 citations·filing 1999–2014
93Inventor score
Top patents by PatentIndex Score
20 records- 0193US7253663B2Apparatus and methods for self-biasing differential signaling circuitry having multimode output configurations for low voltage applicationsATI TECHNOLOGIES INC·Filed 2005·Granted Aug 7, 2007·23 cites·26 claims
- 0289US7319358B2Method and apparatus for generating an adaptive power supply voltageATI TECHNOLOGIES INC·Filed 2005·Granted Jan 15, 2008·26 cites·20 claims
- 0378US8286022B2Intra-pair differential skew compensation method and apparatus for high-speed cable data transmission systemsFUNG RICHARD·Filed 2009·Granted Oct 9, 2012·10 cites·12 claims
- 0472US7495477B2Apparatus and methods for self-biasing differential signaling circuitry having multimode output configurations for low voltage applicationsATI TECHNOLOGIES INC·Filed 2007·Granted Feb 24, 2009·5 cites·20 claims
- 0572US7493509B2Intra-pair differential skew compensation method and apparatus for high-speed cable data transmission systemsATI TECHNOLOGIES ULC·Filed 2004·Granted Feb 17, 2009·15 cites·26 claims
- 0671US7336212B2Apparatus and methods for measurement of analog voltages in an integrated circuitATI TECHNOLOGIES INC·Filed 2005·Granted Feb 26, 2008·7 cites·21 claims
- 0770US8330476B2Dynamic voltage and power management by temperature monitoringCHAN NANCY·Filed 2005·Granted Dec 11, 2012·7 cites·11 claims
- 0869US7724037B2Apparatus and methods for self-biasing differential signaling circuitry having multimode output configurations for low voltage applicationsATI TECHNOLOGIES ULC·Filed 2009·Granted May 25, 2010·4 cites·18 claims
- 0962US7236040B2Method and apparatus for generating multiphase clocksATI TECHNOLOGIES INC·Filed 2004·Granted Jun 26, 2007·10 cites·36 claims
- 1060US8441310B2Power control based on dual loop with multiple process detection circuitsSENTHINATHAN RAMESH·Filed 2011·Granted May 14, 2013·2 cites·20 claims
- 1160US7663426B2Method and apparatus for biasing circuits in response to power up conditionsATI TECHNOLOGIES ULC·Filed 2004·Granted Feb 16, 2010·9 cites·10 claims
- 1259US6601196B1Method and apparatus for debugging ternary and high speed bussesINTEL CORP·Filed 2000·Granted Jul 29, 2003·8 cites·27 claims
- 1355US8618866B2Apparatus and methods for balancing supply voltagesFUNG RICHARD W·Filed 2005·Granted Dec 31, 2013·4 cites·8 claims
- 1450US9013851B2Inrush current control circuit and method for utilizing sameKIDD DAVID ANTHONY·Filed 2010·Granted Apr 21, 2015·1 cites·20 claims
- 1548US2006123177A1Method and apparatus for transporting and interoperating transition minimized differential signaling over differential serial communication transmittersATI TECHNOLOGIES INC·Filed 2004·Application pending·0 cites
- 1646US2011066778A1Method and apparatus for transporting and interoperating transition minimized differential signaling over differential serial communication transmittersATI TECHNOLOGIES ULC·Filed 2010·Application pending·0 cites
- 1746US2011060847A1Method and apparatus for transporting and interoperating transition minimized differential signaling over differential serial communication transmittersATI TECHNOLOGIES ULC·Filed 2010·Application pending·0 cites
- 1840US2015177821A1Multiple Execution Unit Processor CoreBROADCOM CORP·Filed 2014·Application pending·0 cites
- 1935US6777975B1Input-output bus interface to bridge different process technologiesINTEL CORP·Filed 1999·Granted Aug 17, 2004·7 cites·12 claims
- 2029US9455722B2Method and apparatus for fast locking of a clock generating circuitLAM SHIRLEY·Filed 2005·Granted Sep 27, 2016·0 cites·30 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →