Inventor · disambiguated record
Rajen Murugan
Also filed as: MURUGAN RAJEN · MURUGAN RAJEN J
5 granted patents·3 pending applications·10 citations·filing 2003–2007
70Inventor score
Files withDELL PRODUCTS LP8
Top patents by PatentIndex Score
8 records- 0171US7680226B2Minimizing dynamic crosstalk-induced jitter timing skewDELL PRODUCTS LP·Filed 2005·Granted Mar 16, 2010·6 cites·16 claims
- 0252US2007217168A1Method, System And Apparatus For Controlled Impedance At Transitional Plated-Through Hole Via Sites Using Barrel Inductance MinimizationDELL PRODUCTS LP·Filed 2007·Application pending·0 cites
- 0350US7889785B2Method, system and apparatus for quantifying the contribution of inter-symbol interference jitter on timing skew budgetDELL PRODUCTS LP·Filed 2007·Granted Feb 15, 2011·0 cites·20 claims
- 0450US7596482B2System and method to analyze and determine ampacity risks on PCB interconnectionsDELL PRODUCTS LP·Filed 2006·Granted Sep 29, 2009·1 cites·18 claims
- 0547US7251302B2Method, system and apparatus for quantifying the contribution of inter-symbol interference jitter on timing skew budgetDELL PRODUCTS LP·Filed 2003·Granted Jul 31, 2007·3 cites·21 claims
- 0645US2007244684A1Method to model 3-D PCB PTH viaDELL PRODUCTS LP·Filed 2006·Application pending·0 cites
- 0742US2005231927A1Method, system and apparatus for controlled impedance at transitional plated-through hole via sites using barrel inductance minimizationDELL PRODUCTS LP·Filed 2004·Application pending·0 cites
- 0839US7577203B2Minimizing non-deterministic noise by using wavelet transformDELL PRODUCTS LP·Filed 2005·Granted Aug 18, 2009·0 cites·23 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →