Inventor · disambiguated record
Kanwal Jit Singh
Also filed as: SINGH KANWAL · SINGH KANWAL JIT
24 granted patents·4 pending applications·192 citations·filing 2009–2022
95Inventor score
Top patents by PatentIndex Score
28 records- 0197US9041217B1Self-aligned via patterning with multi-colored photobuckets for back end of line (BEOL) interconnectsBRISTOL ROBERT L·Filed 2013·Granted May 26, 2015·53 cites·5 claims
- 0295US9406512B2Self-aligned via patterning with multi-colored photobuckets for back end of line (BEOL) interconnectsBRISTOL ROBERT L·Filed 2015·Granted Aug 2, 2016·16 cites·16 claims
- 0394US9236342B2Self-aligned via and plug patterning with photobuckets for back end of line (BEOL) interconnectsBRISTOL ROBERT L·Filed 2013·Granted Jan 12, 2016·21 cites·20 claims
- 0493US10032643B2Method and structure to contact tight pitch conductive layers with guided vias using alternating hardmasks and encapsulating etchstop liner schemeINTEL CORP·Filed 2014·Granted Jul 24, 2018·16 cites·25 claims
- 0592US8772938B2Semiconductor interconnect structuresBOYANOV BOYAN·Filed 2012·Granted Jul 8, 2014·13 cites·23 claims
- 0690US9754886B2Semiconductor interconnect structuresINTEL CORP·Filed 2016·Granted Sep 5, 2017·5 cites·20 claims
- 0790US9064872B2Semiconductor interconnect structuresINTEL CORP·Filed 2014·Granted Jun 23, 2015·8 cites·20 claims
- 0889US9548269B2Diagonal hardmasks for improved overlay in fabricating back end of line (BEOL) interconnectsMYERS ALAN M·Filed 2015·Granted Jan 17, 2017·7 cites·9 claims
- 0989US9209077B2Diagonal hardmasks for improved overlay in fabricating back end of line (BEOL) interconnectsMYERS ALAN M·Filed 2013·Granted Dec 8, 2015·10 cites·17 claims
- 1088US9627321B2Methods and apparatuses to form self-aligned capsINTEL CORP·Filed 2015·Granted Apr 18, 2017·4 cites·9 claims
- 1188US9406615B2Techniques for forming interconnects in porous dielectric materialsINTEL CORP·Filed 2013·Granted Aug 2, 2016·6 cites·25 claims
- 1286US8080475B2Removal chemistry for selectively etching metal hard maskRAMACHANDRARAO VIJAYAKUMAR SUBRAMANYARAO·Filed 2009·Granted Dec 20, 2011·16 cites·16 claims
- 1383US9455224B2Semiconductor interconnect structuresINTEL CORP·Filed 2015·Granted Sep 27, 2016·3 cites·20 claims
- 1481US9553018B2Self-aligned via and plug patterning with photobuckets for back end of line (BEOL) interconnectsINTEL CORP·Filed 2015·Granted Jan 24, 2017·3 cites·11 claims
- 1577US9379010B2Methods for forming interconnect layers having tight pitch interconnect structuresINTEL CORP·Filed 2014·Granted Jun 28, 2016·4 cites·22 claims
- 1677US2022270978A1Methods and apparatuses to form self-aligned capsINTEL CORP·Filed 2022·Application pending·0 cites
- 1774US10446493B2Methods and apparatuses to form self-aligned capsINTEL CORP·Filed 2017·Granted Oct 15, 2019·1 cites·7 claims
- 1873US9373584B2Methods and apparatuses to form self-aligned capsBOYANOV BOYAN·Filed 2011·Granted Jun 21, 2016·2 cites·11 claims
- 1971US2020321282A1Methods and apparatuses to form self-aligned capsINTEL CORP·Filed 2020·Application pending·0 cites
- 2068US9565766B2Formation of DRAM capacitor among metal interconnectLINDERT NICK·Filed 2011·Granted Feb 7, 2017·2 cites·31 claims
- 2164US10727183B2Methods and apparatuses to form self-aligned capsINTEL CORP·Filed 2019·Granted Jul 28, 2020·0 cites·25 claims
- 2264US10147639B2Via self alignment and shorting improvement with airgap integration capacitance benefitINTEL CORP·Filed 2014·Granted Dec 4, 2018·1 cites·17 claims
- 2359US9659869B2Forming barrier walls, capping, or alloys /compounds within metal linesINTEL CORP·Filed 2012·Granted May 23, 2017·1 cites·13 claims
- 2454US9887161B2Techniques for forming interconnects in porous dielectric materialsINTEL CORP·Filed 2016·Granted Feb 6, 2018·0 cites·20 claims
- 2548US2017148868A1Formation of dram capacitor among metal interconnectINTEL CORP·Filed 2017·Application pending·0 cites
- 2644US10593627B2Doric pillar supported maskless airgap structure for capacitance benefit with unlanded via solutionINTEL CORP·Filed 2015·Granted Mar 17, 2020·0 cites·11 claims
- 2743US10457548B2Integrating MEMS structures with interconnects and viasINTEL CORP·Filed 2015·Granted Oct 29, 2019·0 cites·21 claims
- 2840US2013292797A1Fully encapsulated conductive linesLINDERT NICK·Filed 2011·Application pending·0 cites
Join the waitlist — get patent alerts
Get an alert when Kanwal Jit Singh files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →