Inventor · disambiguated record
Jongwook Kye
Also filed as: KYE JONGWOOK
88 granted patents·5 pending applications·948 citations·filing 2000–2018
99Inventor score
Files withGLOBALFOUNDRIES INC51ADVANCED MICRO DEVICES INC20YUAN LEI8RASHED MAHBUB3ADVANCED MICRO DEVICES IN1
Top patents by PatentIndex Score
93 records- 0198US7315033B1Method and apparatus for reducing biological contamination in an immersion lithography systemADVANCED MICRO DEVICES INC·Filed 2005·Granted Jan 1, 2008·65 cites·20 claims
- 0297US9437588B1Middle of-line architecture for dense library layout using M0 hand-shakeGLOBALFOUNDRIES INC·Filed 2015·Granted Sep 6, 2016·26 cites·13 claims
- 0397US8954913B1Methods of generating circuit layouts that are to be manufactured using SADP routing techniques and virtual non-mandrel mask rulesGLOBALFOUNDRIES INC·Filed 2013·Granted Feb 10, 2015·43 cites·12 claims
- 0496US9437481B2Self-aligned double patterning process for two dimensional patternsGLOBALFOUNDRIES INC·Filed 2015·Granted Sep 6, 2016·15 cites·20 claims
- 0596US9431300B1MOL architecture enabling ultra-regular cross coupleGLOBALFOUNDRIES INC·Filed 2015·Granted Aug 30, 2016·18 cites·20 claims
- 0696US9324722B1Utilization of block-mask and cut-mask for forming metal routing in an IC deviceGLOBALFOUNDRIES INC·Filed 2015·Granted Apr 26, 2016·16 cites·20 claims
- 0796US6489068B1Process for observing overlay errors on lithographic masksADVANCED MICRO DEVICES INC·Filed 2001·Granted Dec 3, 2002·87 cites·20 claims
- 0895US9818651B2Methods, apparatus and system for a passthrough-based architectureGLOBALFOUNDRIES INC·Filed 2016·Granted Nov 14, 2017·15 cites·10 claims
- 0995US9105510B2Double sidewall image transfer processGLOBALFOUNDRIES INC·Filed 2014·Granted Aug 11, 2015·16 cites·17 claims
- 1095US8921225B2Method for off-grid routing structures utilizing self aligned double patterning (SADP) technologyGLOBALFOUNDRIES INC·Filed 2013·Granted Dec 30, 2014·19 cites·12 claims
- 1195US8889561B2Double sidewall image transfer processWOO YOUNGTAG·Filed 2012·Granted Nov 18, 2014·44 cites·12 claims
- 1294US9202751B2Transistor contacts self-aligned in two dimensionsGLOBALFOUNDRIES INC·Filed 2014·Granted Dec 1, 2015·13 cites·20 claims
- 1394US9147653B2Method for off-grid routing structures utilizing self aligned double patterning (SADP) technologyGLOBALFOUNDRIES INC·Filed 2014·Granted Sep 29, 2015·12 cites·20 claims
- 1494US8881083B1Methods for improving double patterning route efficiencyGLOBALFOUNDRIES INC·Filed 2013·Granted Nov 4, 2014·19 cites·20 claims
- 1594US8741763B2Layout designs with via routing structuresMA YUANSHENG·Filed 2012·Granted Jun 3, 2014·38 cites·17 claims
- 1693US8918746B1Cut mask aware contact enclosure rule for grating and cut patterning solutionGLOBALFOUNDRIES INC·Filed 2013·Granted Dec 23, 2014·19 cites·20 claims
- 1793US8581348B2Semiconductor device with transistor local interconnectsRASHED MAHBUB·Filed 2011·Granted Nov 12, 2013·20 cites·16 claims
- 1892US10147714B2Method, apparatus, and system for two-dimensional power rail to enable scaling of a standard cellGLOBALFOUNDRIES INC·Filed 2016·Granted Dec 4, 2018·9 cites·20 claims
- 1992US9727685B2Method, apparatus, and system for improved standard cell design and routing for improving standard cell routabilityGLOBALFOUNDRIES INC·Filed 2015·Granted Aug 8, 2017·10 cites·19 claims
- 2092US9122830B2Wide pin for improved circuit routingGLOBALFOUNDRIES INC·Filed 2013·Granted Sep 1, 2015·12 cites·20 claims
- 2192US8679911B2Cross-coupling-based design using diffusion contact structuresWANG YAN·Filed 2012·Granted Mar 25, 2014·14 cites·12 claims
- 2291US9679809B1Method of forming self aligned continuity blocks for mandrel and non-mandrel interconnect linesGLOBALFOUNDRIES INC·Filed 2016·Granted Jun 13, 2017·8 cites·15 claims
- 2391US9035679B2Standard cell connection for circuit routingGLOBALFOUNDRIES INC·Filed 2013·Granted May 19, 2015·13 cites·15 claims
- 2490US8802574B2Methods of making jogged layout routings double patterning compliantYUAN LEI·Filed 2012·Granted Aug 12, 2014·11 cites·12 claims
- 2589US9536778B2Self-aligned double patterning process for metal routingGLOBALFOUNDRIES INC·Filed 2015·Granted Jan 3, 2017·6 cites·16 claims
- 2688US8839168B2Self-aligned double patterning via enclosure designGLOBALFOUNDRIES INC·Filed 2013·Granted Sep 16, 2014·11 cites·20 claims
- 2788US6829040B1Lithography contrast enhancement technique by varying focus with wavelength modulationADVANCED MICRO DEVICES INC·Filed 2003·Granted Dec 7, 2004·32 cites·18 claims
- 2887US9472464B1Methods to utilize merged spacers for use in fin generation in tapered IC devicesGLOBALFOUNDRIES INC·Filed 2016·Granted Oct 18, 2016·5 cites·20 claims
- 2987US9159724B2Cross-coupling-based design using diffusion contact structuresGLOBALFOUNDRIES INC·Filed 2014·Granted Oct 13, 2015·8 cites·20 claims
- 3087US9006100B2Middle-of-the-line constructs using diffusion contact structuresRASHED MAHBUB·Filed 2012·Granted Apr 14, 2015·9 cites·14 claims
- 3187US6555274B1Pupil filtering for a lithographic toolFiled 2001·Granted Apr 29, 2003·27 cites·20 claims
- 3286US10366917B2Methods of patterning variable width metallization linesGLOBALFOUNDRIES INC·Filed 2018·Granted Jul 30, 2019·5 cites·20 claims
- 3386US9330221B2Mask-aware routing and resulting deviceGLOBALFOUNDRIES INC·Filed 2014·Granted May 3, 2016·9 cites·15 claims
- 3485US6556286B1Inspection system for the pupil of a lithographic toolADVANCED MICRO DEVICES INC·Filed 2001·Granted Apr 29, 2003·24 cites·20 claims
- 3584US6459480B1Measurement method of Zernike coma aberration coefficientADVANCED MICRO DEVICES INC·Filed 2000·Granted Oct 1, 2002·28 cites·8 claims
- 3683US9041087B2Semiconductor devices having dielectric caps on contacts and related fabrication methodsGLOBALFOUNDRIES INC·Filed 2014·Granted May 26, 2015·5 cites·20 claims
- 3782US8966412B1Methods of generating circuit layouts that are to be manufactured using SADP techniquesGLOBALFOUNDRIES INC·Filed 2013·Granted Feb 24, 2015·6 cites·19 claims
- 3882US6710853B1Phase grating focus monitor using overlay techniqueADVANCED MICRO DEVICES INC·Filed 2001·Granted Mar 23, 2004·22 cites·15 claims
- 3981US9660040B2Transistor contacts self-aligned two dimensionsGLOBALFOUNDRIES INC·Filed 2015·Granted May 23, 2017·2 cites·6 claims
- 4081US8765599B2Semiconductor devices having dielectric caps on contacts and related fabrication methodsYUAN LEI·Filed 2012·Granted Jul 1, 2014·5 cites·20 claims
- 4180US9613177B2Methods of generating circuit layouts that are to be manufactured using SADP routing techniquesGLOBALFOUNDRIES INC·Filed 2014·Granted Apr 4, 2017·4 cites·16 claims
- 4280US9519745B2Method and apparatus for assisted metal routingGLOBALFOUNDRIES INC·Filed 2014·Granted Dec 13, 2016·5 cites·10 claims
- 4380US8735050B2Integrated circuits and methods for fabricating integrated circuits using double patterning processesYUAN LEI·Filed 2012·Granted May 27, 2014·3 cites·18 claims
- 4479US9582629B2Methods of generating circuit layouts using self-alligned double patterning (SADP) techniquesGLOBALFOUNDRIES INC·Filed 2014·Granted Feb 28, 2017·5 cites·9 claims
- 4579US8966423B2Integrating optimal planar and three-dimensional semiconductor design layoutsGLOBALFOUNDARIES INC·Filed 2013·Granted Feb 24, 2015·5 cites·12 claims
- 4679US8677291B1Double patterning compatible colorless M1 routeYUAN LEI·Filed 2012·Granted Mar 18, 2014·6 cites·19 claims
- 4778US9292647B2Method and apparatus for modified cell architecture and the resulting deviceGLOBALFOUNDRIES INC·Filed 2014·Granted Mar 22, 2016·4 cites·18 claims
- 4878US6602794B1Silylation process for forming contactsADVANCED MICRO DEVICES INC·Filed 2001·Granted Aug 5, 2003·20 cites·20 claims
- 4977US9536035B2Wide pin for improved circuit routingGLOBALFOUNDRIES INC·Filed 2015·Granted Jan 3, 2017·2 cites·20 claims
- 5077US8719757B2Method to enhance double patterning routing efficiencyYUAN LEI·Filed 2012·Granted May 6, 2014·4 cites·18 claims
Showing the top 50 of 93 patent records by PatentIndex Score.
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