Inventor · disambiguated record
Andrew Draper
Also filed as: DRAPER ANDREW · DRAPER ANDREW M · DRAPER ANDREW MARTYN
36 granted patents·4 pending applications·631 citations·filing 2000–2025
97Inventor score
Top patents by PatentIndex Score
40 records- 0196US6826717B1Synchronization of hardware and software debuggersALTERA CORP·Filed 2001·Granted Nov 30, 2004·124 cites·39 claims
- 0295US7822958B1Booting mechanism for FPGA-based embedded systemALTERA CORP·Filed 2006·Granted Oct 26, 2010·49 cites·18 claims
- 0393US7340596B1Embedded processor with watchdog timer for programmable logicALTERA CORP·Filed 2001·Granted Mar 4, 2008·101 cites·22 claims
- 0492US8069286B1Flexible on-chip datapath interface having first and second component interfaces wherein communication is determined based on a type of credit conditionORTHNER KENT·Filed 2010·Granted Nov 29, 2011·20 cites·18 claims
- 0591US7350178B1Embedded processor with watchdog timer for programmable logicALTERA CORP·Filed 2004·Granted Mar 25, 2008·61 cites·21 claims
- 0690US10223014B1Maintaining reconfigurable partitions in a programmable deviceINTEL CORP·Filed 2017·Granted Mar 5, 2019·8 cites·20 claims
- 0785US12010144B2End-to-end device attestationINTEL CORP·Filed 2021·Granted Jun 11, 2024·2 cites·28 claims
- 0885US7546424B1Embedded processor with dual-port SRAM for programmable logicALTERA CORP·Filed 2006·Granted Jun 9, 2009·14 cites·24 claims
- 0984US6732263B1Configuring both a programmable logic device and its embedded logic with a single serialized configuration bit streamALTERA CORP·Filed 2000·Granted May 4, 2004·39 cites·11 claims
- 1083US9191617B1Using FPGA partial reconfiguration for codec applicationsALTERA CORP·Filed 2013·Granted Nov 17, 2015·10 cites·20 claims
- 1183US7096324B1Embedded processor with dual-port SRAM for programmable logicALTERA CORP·Filed 2001·Granted Aug 22, 2006·34 cites·20 claims
- 1280US7844761B1Flexible on-chip datapath interface for facilitating communication between first and second interfaces with different interface propertiesALTERA CORP·Filed 2006·Granted Nov 30, 2010·9 cites·24 claims
- 1379US6961884B1JTAG mirroring circuitry and methodsALTERA CORP·Filed 2001·Granted Nov 1, 2005·23 cites·28 claims
- 1478US7078929B1Interface controller using JTAG scan chainALTERA CORP·Filed 2004·Granted Jul 18, 2006·22 cites·13 claims
- 1576US9404968B1System and methods for debug connectivity discoveryALTERA CORP·Filed 2013·Granted Aug 2, 2016·3 cites·25 claims
- 1675US10659052B2Regional partial reconfiguration of a programmable deviceINTEL CORPRORATION·Filed 2019·Granted May 19, 2020·2 cites·20 claims
- 1773US8412918B1Booting mechanism for FPGA-based embedded systemALLEN TIMOTHY P·Filed 2010·Granted Apr 2, 2013·3 cites·22 claims
- 1872US6862724B1Reconfigurable programmable logic system with peripheral identification dataALTERA CORP·Filed 2002·Granted Mar 1, 2005·24 cites·36 claims
- 1972US6828822B1Apparatus and methods for shared memory interfaces in programmable logic devicesALTERA CORP·Filed 2003·Granted Dec 7, 2004·18 cites·42 claims
- 2070US7249222B1Prefetching data based on predetermined criteriaALTERA CORP·Filed 2004·Granted Jul 24, 2007·16 cites·21 claims
- 2162US7343483B1Configuring both a programmable logic device and its embedded logic with a single serialized configuration bit streamALTERA CORP·Filed 2004·Granted Mar 11, 2008·8 cites·20 claims
- 2262US7321996B1Digital data error insertion methods and apparatusALTERA CORP·Filed 2004·Granted Jan 22, 2008·9 cites·19 claims
- 2361US11562101B2On-device bitstream validationINTEL CORP·Filed 2018·Granted Jan 24, 2023·1 cites·21 claims
- 2459US6937061B1Address decoder for programmable logic deviceALTERA CORP·Filed 2003·Granted Aug 30, 2005·7 cites·18 claims
- 2559US2025315538A1Key Store System For Controlling Access To KeysALTERA CORP·Filed 2025·Application pending·0 cites
- 2657US12189775B2Seamless firmware update mechanismINTEL CORP·Filed 2022·Granted Jan 7, 2025·0 cites·20 claims
- 2757US7657689B1Methods and apparatus for handling reset events in a bus bridgeALTERA CORP·Filed 2003·Granted Feb 2, 2010·6 cites·24 claims
- 2857US7584348B1Techniques for configuring an embedded processor operating systemALTERA CORP·Filed 2005·Granted Sep 1, 2009·2 cites·21 claims
- 2954US10218359B2Regional partial reconfiguration of a programmable deviceINTEL CORPRORATION·Filed 2017·Granted Feb 26, 2019·0 cites·21 claims
- 3052US8190828B1Embedded processor with dual-port SRAM for programmable logicMAY ROGER·Filed 2009·Granted May 29, 2012·1 cites·20 claims
- 3152US7263623B1Microprocessor systemALTERA CORP·Filed 2004·Granted Aug 28, 2007·5 cites·19 claims
- 3251US11281383B2Side-channel attack resistant fuse programmingINTEL CORP·Filed 2018·Granted Mar 22, 2022·0 cites·20 claims
- 3350US7549004B1Split filtering in multilayer systemsALTERA CORP·Filed 2004·Granted Jun 16, 2009·6 cites·22 claims
- 3449US2024004810A1Multiple channel direct access memory-based configuration systemINTEL CORP·Filed 2022·Application pending·0 cites
- 3548US12183412B2Method and apparatus for enabling multiple return material authorizations (RMAs) on an integrated circuit deviceINTEL CORP·Filed 2020·Granted Dec 31, 2024·0 cites·20 claims
- 3648US7412624B1Methods and apparatus for debugging a system with a hung data busALTERA CORP·Filed 2004·Granted Aug 12, 2008·4 cites·28 claims
- 3748US2025061203A1Device runtime update pre-authenticationINTEL CORP·Filed 2022·Application pending·0 cites
- 3844US10444283B1Sharing a JTAG interface among multiple partitionsINTEL CORP·Filed 2017·Granted Oct 15, 2019·0 cites·20 claims
- 3939US2019050603A1Programmable device authentication decryptionINTEL CORP·Filed 2018·Application pending·0 cites
- 4030US7064578B1Distributed bus structureALTERA CORP·Filed 2003·Granted Jun 20, 2006·0 cites·19 claims
Join the waitlist — get patent alerts
Get an alert when Andrew Draper files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →