Inventor · disambiguated record
Yung-Huei Lee
Also filed as: LEE YUNG-HUEI
13 granted patents·1 pending application·132 citations·filing 1996–2025
88Inventor score
Top patents by PatentIndex Score
14 records- 0190US11978511B2Phase-change memory cell and method for fabricating the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted May 7, 2024·2 cites·20 claims
- 0285US11972826B2System and method for extending lifetime of memory deviceTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Apr 30, 2024·2 cites·20 claims
- 0384US5633202AHigh tensile nitride layerINTEL CORP·Filed 1996·Granted May 27, 1997·65 cites·11 claims
- 0483US6046494AHigh tensile nitride layerINTEL CORP·Filed 1997·Granted Apr 4, 2000·62 cites·12 claims
- 0581US2025292832A1Phase-change memory cell and method for fabricating the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 0676US12340844B2Phase-change memory cell and method for fabricating the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Granted Jun 24, 2025·0 cites·20 claims
- 0760US10475742B2Method for forming semiconductor device structure having conductive structure with twin boundariesTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2018·Granted Nov 12, 2019·0 cites·20 claims
- 0857US10283450B2Method for forming semiconductor device structure having conductive structure with twin boundariesTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted May 7, 2019·0 cites·21 claims
- 0956US8633109B2Soft error rate (SER) reduction in advanced silicon processesLEE YUNG-HUEI·Filed 2011·Granted Jan 21, 2014·1 cites·20 claims
- 1053US9761523B2Interconnect structure with twin boundaries and method for forming the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted Sep 12, 2017·0 cites·20 claims
- 1150US9941159B2Method of manufacturing a semiconductor deviceTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted Apr 10, 2018·0 cites·20 claims
- 1248US9449919B2Semiconductor device, layout design and method for manufacturing a semiconductor deviceTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted Sep 20, 2016·0 cites·20 claims
- 1343US10431541B2Semiconductor device, layout pattern and method for manufacturing an integrated circuitTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Oct 1, 2019·0 cites·20 claims
- 1434US8946874B2IC in-process solution to reduce thermal neutrons soft error rateLEE YUNG-HUEI·Filed 2011·Granted Feb 3, 2015·0 cites·19 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →