Inventor · disambiguated record
Johnny Widodo
Also filed as: WIDODO JOHNNY
21 granted patents·10 pending applications·90 citations·filing 2006–2011
93Inventor score
Files withCHARTERED SEMICONDUCTOR MFG12SAMSUNG ELECTRONICS CO LTD6GLOBALFOUNDRIES SG PTE LTD4TEO LEE WEE2WIDODO JOHNNY2
Top patents by PatentIndex Score
31 records- 0193US7524755B2Entire encapsulation of Cu interconnects using self-aligned CuSiN filmCHARTERED SEMICONDUCTOR MFG·Filed 2006·Granted Apr 28, 2009·37 cites·18 claims
- 0287US7566656B2Method and apparatus for providing void structuresCHARTERED SEMICONDUCTOR MFG·Filed 2006·Granted Jul 28, 2009·17 cites·31 claims
- 0372US7923365B2Methods of forming field effect transistors having stress-inducing sidewall insulating spacers thereonSAMSUNG ELECTRONICS CO LTD·Filed 2007·Granted Apr 12, 2011·4 cites·15 claims
- 0470US7847402B2BEOL interconnect structures with improved resistance to stressIBM·Filed 2007·Granted Dec 7, 2010·4 cites·13 claims
- 0569US8716081B2Capacitor top plate over source/drain to form a 1T memory deviceTEO LEE WEE·Filed 2007·Granted May 6, 2014·4 cites·29 claims
- 0669US8274115B2Hybrid orientation substrate with stress layerTEO LEE WEE·Filed 2008·Granted Sep 25, 2012·4 cites·16 claims
- 0768US7838390B2Methods of forming integrated circuit devices having ion-cured electrically insulating layers thereinSAMSUNG ELECTRONICS CO LTD·Filed 2007·Granted Nov 23, 2010·4 cites·7 claims
- 0867US7687381B2Method of forming electrical interconnects within insulating layers that form consecutive sidewalls including forming a reaction layer on the inner sidewallSAMSUNG ELECTRONICS CO LTD·Filed 2008·Granted Mar 30, 2010·4 cites·18 claims
- 0966US8178417B2Method of forming shallow trench isolation structures for integrated circuitsMISHRA SHAILENDRA·Filed 2008·Granted May 15, 2012·4 cites·23 claims
- 1066US8053327B2Method of manufacture of an integrated circuit system with self-aligned isolation structuresGLOBALFOUNDRIES SG PTE LTD·Filed 2006·Granted Nov 8, 2011·3 cites·10 claims
- 1166US7541288B2Methods of forming integrated circuit structures using insulator deposition and insulator gap filling techniquesSAMSUNG ELECTRONICS CO LTD·Filed 2007·Granted Jun 2, 2009·2 cites·23 claims
- 1265US7622403B2Semiconductor processing system with ultra low-K dielectricCHARTERED SEMICONDUCTOR MFG·Filed 2006·Granted Nov 24, 2009·2 cites·10 claims
- 1357US7459388B2Methods of forming dual-damascene interconnect structures using adhesion layers having high internal compressive stressesSAMSUNG ELECTRONICS CO LTD·Filed 2006·Granted Dec 2, 2008·1 cites·19 claims
- 1450US7767577B2Nested and isolated transistors with reduced impedance differenceCHARTERED SEMICONDUCTOR MFG·Filed 2008·Granted Aug 3, 2010·0 cites·18 claims
- 1548US7795680B2Integrated circuit system employing selective epitaxial growth technologyCHARTERED SEMICONDUCTOR MFG·Filed 2007·Granted Sep 14, 2010·0 cites·20 claims
- 1648US7737029B2Methods of forming metal interconnect structures on semiconductor substrates using oxygen-removing plasmas and interconnect structures formed therebySAMSUNG ELECTRONICS CO LTD·Filed 2008·Granted Jun 15, 2010·0 cites·18 claims
- 1747US7999300B2Memory cell structure and method for fabrication thereofGLOBALFOUNDRIES SG PTE LTD·Filed 2009·Granted Aug 16, 2011·0 cites·22 claims
- 1847US2010009527A1Integrated circuit system employing single mask layer technique for well formationCHARTERED SEMICONDUCTOR MFG·Filed 2008·Application pending·0 cites
- 1945US2009315115A1Implantation for shallow trench isolation (STI) formation and for stress for transistor performance enhancementCHARTERED SEMICONDUCTOR MFG·Filed 2008·Application pending·0 cites
- 2044US7906426B2Method of controlled low-k via etch for Cu interconnectionsGLOBALFOUNDRIES SG PTE LTD·Filed 2007·Granted Mar 15, 2011·0 cites·17 claims
- 2144US7829422B2Integrated circuit having ultralow-K dielectric layerCHARTERED SEMICONDUCTOR MFG·Filed 2006·Granted Nov 9, 2010·0 cites·24 claims
- 2244US2008230907A1Integrated circuit system with carbon enhancementCHARTERED SEMICONDUCTOR MFG·Filed 2007·Application pending·0 cites
- 2342US2010109155A1Reliable interconnect integrationCHARTERED SEMICONDUCTOR MFG·Filed 2008·Application pending·0 cites
- 2441US8143651B2Nested and isolated transistors with reduced impedance differenceWIDODO JOHNNY·Filed 2010·Granted Mar 27, 2012·0 cites·19 claims
- 2541US7932178B2Integrated circuit having a plurality of MOSFET devicesGLOBALFOUNDRIES SG PTE LTD·Filed 2006·Granted Apr 26, 2011·0 cites·6 claims
- 2640US2008044967A1Integrated circuit system having strained transistorCHARTERED SEMICONDUCTOR MFG·Filed 2006·Application pending·0 cites
- 2739US2011156110A1Field Effect Transistors Having Gate Electrode Silicide Layers with Reduced Surface DamageKIM JUN-JUNG·Filed 2011·Application pending·0 cites
- 2838US2007249128A1Ultraviolet (UV) Radiation Treatment Methods for Subatmospheric Chemical Vapor Deposition (SACVD) of Ozone-Tetraethoxysilane (O3-TEOS)KIM JUNJUNG·Filed 2006·Application pending·0 cites
- 2938US2009050972A1Strained Semiconductor Device and Method of Making SameLINDSAY RICHARD·Filed 2007·Application pending·0 cites
- 3038US2009325359A1Integrated circuit system employing a modified isolation structureCHARTERED SEMICONDUCTOR MFG·Filed 2008·Application pending·0 cites
- 3136US2008124855A1Modulation of Stress in ESL SiN Film through UV Curing to Enhance both PMOS and NMOS Transistor PerformanceWIDODO JOHNNY·Filed 2006·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →