Inventor · disambiguated record
Massimo Sutera
Also filed as: CAPELLANO IVANA · SUTERA MASSIMO
14 granted patents·72 citations·filing 1999–2024
88Inventor score
Top patents by PatentIndex Score
14 records- 0197US12204410B2Integrated error correction code (ECC) and parity protection in memory control circuits for increased memory utilizationAMPERE COMPUTING LLC·Filed 2022·Granted Jan 21, 2025·14 cites·25 claims
- 0290US7721011B1Method and apparatus for reordering memory accesses to reduce power consumption in computer systemsORACLE AMERICA INC·Filed 2005·Granted May 18, 2010·30 cites·26 claims
- 0386US11934263B2Parity protected memory blocks merged with error correction code (ECC) protected blocks in a codeword for increased memory utilizationAMPERE COMPUTING LLC·Filed 2022·Granted Mar 19, 2024·1 cites·24 claims
- 0475US12314130B2Parity protected memory blocks merged with error correction code (ECC) protected blocks in a codeword for increased memory utilizationAMPERE COMPUTING LLC·Filed 2024·Granted May 27, 2025·0 cites·17 claims
- 0574US9734054B1Efficient implementation of geometric seriesINTEL CORP·Filed 2016·Granted Aug 15, 2017·2 cites·20 claims
- 0667US12474848B2Techniques for memory resource control using memory resource partitioning and monitoringAMPERE COMPUTING LLC·Filed 2023·Granted Nov 18, 2025·0 cites·20 claims
- 0757US6900674B2Method and circuitry for phase align detection in multi-clock domainSUN MICROSYSTEMS INC·Filed 2003·Granted May 31, 2005·7 cites·39 claims
- 0855US12159056B2Extending functionality of memory controllers in a processor-based deviceAMPERE COMPUTING LLC·Filed 2022·Granted Dec 3, 2024·0 cites·19 claims
- 0955US10042562B2Apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory deviceINTEL CORP·Filed 2017·Granted Aug 7, 2018·0 cites·20 claims
- 1052US9747041B2Apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory deviceINTEL CORP·Filed 2015·Granted Aug 29, 2017·0 cites·25 claims
- 1151US12451206B2Extending functionality of memory controllers using a loopback mode for testing in a processor-based deviceAMPERE COMPUTING LLC·Filed 2023·Granted Oct 21, 2025·0 cites·20 claims
- 1247US10007606B2Implementation of reserved cache slots in computing system having inclusive/non inclusive tracking and two level system memoryINTEL CORP·Filed 2016·Granted Jun 26, 2018·0 cites·21 claims
- 1345US6832180B1Method for reducing noise in integrated circuit layoutsSUN MICROSYSTEMS INC·Filed 1999·Granted Dec 14, 2004·18 cites·22 claims
- 1439US10162750B2System address reconstructionINTEL CORP·Filed 2015·Granted Dec 25, 2018·0 cites·24 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →