Inventor · disambiguated record

Bret Siarowski

Also filed as: SIAROWSKI BRET

2 granted patents·0 citations·filing 2007–2007

31Inventor score

Technology areasG06F

Files withCADENCE DESIGN SYSTEMS INC2

Top patents by PatentIndex Score

2 records

0148US7620919B2Method and system for logic equivalence checkingCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted Nov 17, 2009·0 cites·17 claims
0248US7620918B2Method and system for logic equivalence checkingCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted Nov 17, 2009·0 cites·25 claims

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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →