Inventor · disambiguated record
Peivand Tehrani
Also filed as: TEHRANI PEIVAND · TEHRANI PEIVAND FALLAH
13 granted patents·3 pending applications·34 citations·filing 2005–2023
88Inventor score
Technology areasG06F
Top patents by PatentIndex Score
16 records- 0190US11222155B1Method and apparatus for reducing pessimism of graph based static timing analysisSYNOPSYS INC·Filed 2020·Granted Jan 11, 2022·4 cites·24 claims
- 0273US9026965B2Arrival edge usage in timing analysisSYNOPSYS INC·Filed 2013·Granted May 5, 2015·5 cites·34 claims
- 0373US8468479B2Consistent hierarchical timing model with crosstalk considerationTEHRANI PEIVAND·Filed 2011·Granted Jun 18, 2013·5 cites·21 claims
- 0473US7272807B2Determining equivalent waveforms for distorted waveformsSYNOPSYS INC·Filed 2005·Granted Sep 18, 2007·7 cites·19 claims
- 0568US8219952B2Variation aware victim and aggressor timing overlap detection by pessimism reduction based on relative positions of timing windowsTEHRANI PEIVAND·Filed 2009·Granted Jul 10, 2012·8 cites·22 claims
- 0665US11288426B2Analyzing delay variations and transition time variations for electronic circuitsSYNOPSYS INC·Filed 2020·Granted Mar 29, 2022·0 cites·20 claims
- 0763US8336013B2Determining an order for visiting circuit blocks in a circuit design for fixing design requirement violationsOH NAHMSUK·Filed 2010·Granted Dec 18, 2012·2 cites·18 claims
- 0862US7861198B2Distorted waveform propagation and crosstalk delay analysis using multiple cell modelsSYNOPSYS INC·Filed 2007·Granted Dec 28, 2010·2 cites·24 claims
- 0961US10783301B2Analyzing delay variations and transition time variations for electronic circuitsSYNOPSYS INC·Filed 2019·Granted Sep 22, 2020·0 cites·20 claims
- 1057US11663384B1Timing modeling of multi-stage cells using both behavioral and structural modelsSYNOPSYS INC·Filed 2021·Granted May 30, 2023·0 cites·18 claims
- 1153US10255395B2Analyzing delay variations and transition time variations for electronic circuitsSYNOPSYS INC·Filed 2016·Granted Apr 9, 2019·0 cites·23 claims
- 1251US2024249053A1Timing analysis in stacked diesSYNOPSYS INC·Filed 2023·Application pending·0 cites
- 1349US9424380B2Augmented simulation method for waveform propagation in delay calculationSYNOPSYS INC·Filed 2014·Granted Aug 23, 2016·0 cites·19 claims
- 1447US8341574B2Crosstalk time-delay analysis using random variablesGANDIKOTA RAVIKISHORE·Filed 2009·Granted Dec 25, 2012·1 cites·22 claims
- 1544US2024143878A1Delay calculation with pattern matching for static timing analysisSYNOPSYS INC·Filed 2022·Application pending·0 cites
- 1643US2022398369A1Enhanced Cell Modeling for Waveform PropagationSYNOPSYS INC·Filed 2021·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →