Inventor · disambiguated record
Kristopher H. Gaewsky
Also filed as: GAEWSKY KRISTOPHER · GAEWSKY KRISTOPHER H
17 granted patents·5 pending applications·51 citations·filing 2012–2025
90Inventor score
Files withINTEL CORP15Intel NDTM US LLC4MICRON TECHNOLOGY INC2SK HYNIX NAND PRODUCT SOLUTIONS CORP DBA SOLIDIGM1
Top patents by PatentIndex Score
22 records- 0194US10224107B1Method and apparatus for dynamically determining start program voltages for a memory deviceINTEL CORP·Filed 2017·Granted Mar 5, 2019·22 cites·20 claims
- 0293US9208888B1Techniques for improving reliability and performance of partially written memory blocks in modern flash memory systemsINTEL CORP·Filed 2014·Granted Dec 8, 2015·15 cites·12 claims
- 0384US10509597B2Memory block access modes for a storage deviceINTEL CORP·Filed 2018·Granted Dec 17, 2019·8 cites·20 claims
- 0477US11462273B2SSD with reduced secure erase time and endurance stressINTEL CORP·Filed 2020·Granted Oct 4, 2022·2 cites·15 claims
- 0573US2025342886A1Read latency reduction for partially-programmed block of non-volatile memoryIntel NDTM US LLC·Filed 2025·Application pending·0 cites
- 0664US9543019B2Error corrected pre-read for upper page write in a multi-level cell memoryINTEL CORP·Filed 2012·Granted Jan 10, 2017·3 cites·13 claims
- 0759US12379989B2Zero voltage program state detectionIntel NDTM US LLC·Filed 2023·Granted Aug 5, 2025·0 cites·20 claims
- 0858US10354738B2One check fail byte (CFBYTE) schemeMICRON TECHNOLOGY INC·Filed 2017·Granted Jul 16, 2019·1 cites·20 claims
- 0956US12243590B2Method and apparatus for improving write uniformity in a memory deviceINTEL CORP·Filed 2021·Granted Mar 4, 2025·0 cites·20 claims
- 1053US12362016B2Read latency reduction for partially-programmed block of non-volatile memoryIntel NDTM US LLC·Filed 2020·Granted Jul 15, 2025·0 cites·21 claims
- 1151US9236136B2Lower page read for multi-level cell memoryINTEL CORP·Filed 2012·Granted Jan 12, 2016·0 cites·19 claims
- 1251US2023099202A1Ssd with reduced secure erase time and endurance stressSK HYNIX NAND PRODUCT SOLUTIONS CORP DBA SOLIDIGM·Filed 2022·Application pending·0 cites
- 1348US10229057B2Method and apparatus for avoiding bus contention after initialization failureINTEL CORP·Filed 2016·Granted Mar 12, 2019·0 cites·17 claims
- 1447US10714186B2Method and apparatus for dynamically determining start program voltages for a memory deviceINTEL CORP·Filed 2019·Granted Jul 14, 2020·0 cites·20 claims
- 1546US10762974B2One check fail byte (CFBYTE) schemeMICRON TECHNOLOGY INC·Filed 2019·Granted Sep 1, 2020·0 cites·20 claims
- 1645US9471488B2Techniques for improving reliability and performance of partially written memory blocks in modern flash memory systemsINTEL CORP·Filed 2015·Granted Oct 18, 2016·0 cites·20 claims
- 1744US2023266910A1Method and apparatus to select a plane in a nand flash die to store a read-only reserved blockIntel NDTM US LLC·Filed 2022·Application pending·0 cites
- 1841US10340024B2Solid state drive physical block revectoring to improve cluster failure ratesINTEL CORP·Filed 2017·Granted Jul 2, 2019·0 cites·24 claims
- 1941US9524774B2Lower page read for multi-level cell memoryINTEL CORP·Filed 2015·Granted Dec 20, 2016·0 cites·18 claims
- 2041US2023044991A1Page map renumbering to reduce error correction failures and improve program time uniformityINTEL CORP·Filed 2021·Application pending·0 cites
- 2133US11163480B2Method and apparatus for performing an erase operation comprising a sequence of micro-pulses in a memory deviceINTEL CORP·Filed 2020·Granted Nov 2, 2021·0 cites·9 claims
- 2231US2019034330A1Mass storage device with dynamic single level cell (slc) buffer specific program and/or erase settingsINTEL CORP·Filed 2017·Application pending·0 cites
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →