Inventor · disambiguated record
Dean Mulla
Also filed as: MULLA DEAN · MULLA DEAN A · MULLA DEAN AHMAD
47 granted patents·5 pending applications·1,383 citations·filing 1994–2024
98Inventor score
Files withINTEL CORP26HEWLETT PACKARD CO9HEWLETT PACKARD DEVELOPMENT CO7INST THE DEV OF EMERGING ARCHI3GARG VIVEK1
Top patents by PatentIndex Score
52 records- 0196US6948094B2Method of correcting a machine check errorINTEL CORP·Filed 2001·Granted Sep 20, 2005·296 cites·20 claims
- 0292US9910470B2Controlling telemetry data communication in a processorINTEL CORP·Filed 2015·Granted Mar 6, 2018·10 cites·16 claims
- 0390US12093100B2Hierarchical power management apparatus and methodINTEL CORP·Filed 2020·Granted Sep 17, 2024·3 cites·15 claims
- 0490US6427188B1Method and system for early tag accesses for lower-level caches in parallel with first-level cacheHEWLETT PACKARD CO·Filed 2000·Granted Jul 30, 2002·67 cites·20 claims
- 0589US9710041B2Masking a power state of a core of a processorINTEL CORP·Filed 2015·Granted Jul 18, 2017·7 cites·21 claims
- 0687US6539457B1Cache address conflict mechanism without store buffersHEWLETT PACKARD CO·Filed 2000·Granted Mar 25, 2003·58 cites·22 claims
- 0780US6557078B1Cache chain structure to implement high bandwidth low latency cache memory subsystemHEWLETT PACKARD DEVELOPMENT CO·Filed 2000·Granted Apr 29, 2003·32 cites·25 claims
- 0879US9501129B2Dynamically adjusting power of non-core processor circuitry including buffer circuitryINTEL CORP·Filed 2013·Granted Nov 22, 2016·4 cites·18 claims
- 0979US6687262B1Distributed MUX scheme for bi-endian rotator circuitHEWLETT PACKARD DEVELOPMENT CO·Filed 2000·Granted Feb 3, 2004·31 cites·16 claims
- 1079US6185660B1Pending access queue for providing data to a target register during an intermediate pipeline phase after a computer cache missHEWLETT PACKARD CO·Filed 1997·Granted Feb 6, 2001·84 cites·4 claims
- 1178US7376877B2Combined tag and data ECC for enhanced soft error recovery from cache tag errorsINTEL CORP·Filed 2004·Granted May 20, 2008·22 cites·24 claims
- 1278US6507892B1L1 cache memoryHEWLETT PACKARD CO·Filed 2000·Granted Jan 14, 2003·28 cites·18 claims
- 1378US5652859AMethod and apparatus for handling snoops in multiprocessor caches having internal buffer queuesINST THE DEV OF EMERGING ARCHI·Filed 1995·Granted Jul 29, 1997·84 cites·8 claims
- 1477US6772383B1Combined tag and data ECC for enhanced soft error recovery from cache tag errorsINTEL CORP·Filed 1999·Granted Aug 3, 2004·68 cites·27 claims
- 1576US6427189B1Multiple issue algorithm with over subscription avoidance feature to get high bandwidth through cache pipelineHEWLETT PACKARD CO·Filed 2000·Granted Jul 30, 2002·25 cites·20 claims
- 1674US6591393B1Masking error detection/correction latency in multilevel cache transfersHEWLETT PACKARD DEVELOPMENT CO·Filed 2000·Granted Jul 8, 2003·17 cites·20 claims
- 1773US5577227AMethod for decreasing penalty resulting from a cache miss in multi-level cache systemFiled 1994·Granted Nov 19, 1996·68 cites·12 claims
- 1872US7159046B2Method and apparatus for configuring communication between devices in a computer systemINTEL CORP·Filed 2004·Granted Jan 2, 2007·17 cites·11 claims
- 1971US6272597B1Dual-ported, pipelined, two level cache systemINTEL CORP·Filed 1998·Granted Aug 7, 2001·60 cites·29 claims
- 2071US2025076954A1Hierarchical power management apparatus and methodINTEL CORP·Filed 2024·Application pending·0 cites
- 2170US5664148ACache arrangement including coalescing buffer queue for non-cacheable dataINST THE DEV OF EMERGING ARCHI·Filed 1995·Granted Sep 2, 1997·59 cites·8 claims
- 2269US6418521B1Hierarchical fully-associative-translation lookaside buffer structureINTEL CORP·Filed 1998·Granted Jul 9, 2002·60 cites·22 claims
- 2367US9753525B2Systems and methods for core droop mitigation based on license stateINTEL CORP·Filed 2014·Granted Sep 5, 2017·2 cites·25 claims
- 2467US6704820B1Unified cache port consolidationHEWLETT PACKARD DEVELOPMENT CO·Filed 2000·Granted Mar 9, 2004·13 cites·26 claims
- 2566US10946866B2Core tightly coupled lockstep for high functional safetyINTEL CORP·Filed 2018·Granted Mar 16, 2021·1 cites·22 claims
- 2666US6647464B2System and method utilizing speculative cache access for improved performanceHEWLETT PACKARD DEVELOPMENT CO·Filed 2000·Granted Nov 11, 2003·13 cites·32 claims
- 2762US6725339B2Processing ordered data requests to a memoryINTEL CORP·Filed 2002·Granted Apr 20, 2004·7 cites·28 claims
- 2862US6105115AMethod and apparatus for managing a memory arrayINTEL CORP·Filed 1997·Granted Aug 15, 2000·39 cites·18 claims
- 2962US5860095AConflict cache having cache miscounters for a computer memory systemHEWLETT PACKARD CO·Filed 1996·Granted Jan 12, 1999·40 cites·6 claims
- 3059US11016556B2Instruction and logic for parallel multi-step power management flowINTEL CORP·Filed 2019·Granted May 25, 2021·0 cites·18 claims
- 3159US6470374B1Carry look-ahead for bi-endian adderHEWLETT PACKARD CO·Filed 2000·Granted Oct 22, 2002·8 cites·20 claims
- 3258US6226763B1Method and apparatus for performing cache accessesINTEL CORP·Filed 1998·Granted May 1, 2001·33 cites·11 claims
- 3356US6874116B2Masking error detection/correction latency in multilevel cache transfersHEWLETT PACKARD DEVELOPMENT CO·Filed 2003·Granted Mar 29, 2005·4 cites·19 claims
- 3453US5870387AMethod and apparatus for initializing a ringHEWLETT PACKARD CO·Filed 1996·Granted Feb 9, 1999·26 cites·28 claims
- 3552US10365707B2Instruction and logic for parallel multi-step power management flowINTEL CORP·Filed 2016·Granted Jul 30, 2019·0 cites·23 claims
- 3650US7680990B2Superword memory-access instructions for data processorHEWLETT PACKARD DEVELOPMENT CO·Filed 2003·Granted Mar 16, 2010·1 cites·13 claims
- 3750US7376775B2Apparatus, system, and method to enable transparent memory hot plug/removeINTEL CORP·Filed 2003·Granted May 20, 2008·2 cites·24 claims
- 3850US6832308B1Apparatus and method for instruction fetch unitINTEL CORP·Filed 2000·Granted Dec 14, 2004·5 cites·48 claims
- 3950US6826573B1Method and apparatus for queue issue pointerINTEL CORP·Filed 2000·Granted Nov 30, 2004·4 cites·54 claims
- 4048US5696939AApparatus and method using a semaphore buffer for semaphore instructionsHEWLETT PACKARD CO·Filed 1995·Granted Dec 9, 1997·21 cites·9 claims
- 4147US8914650B2Dynamically adjusting power of non-core processor circuitry including buffer circuitrySISTLA KRISHNAKANTH·Filed 2011·Granted Dec 16, 2014·0 cites·18 claims
- 4247US6381678B2Processing ordered data requests to a memoryINTEL CORP·Filed 1998·Granted Apr 30, 2002·17 cites·16 claims
- 4345US9720491B2Tracking missed periodic actions across state domainsINTEL CORP·Filed 2015·Granted Aug 1, 2017·0 cites·20 claims
- 4444US2005289435A1Fast approximate DINV calculation in parallel with coupled ECC generation or correctionMULLA DEAN A·Filed 2004·Application pending·0 cites
- 4543US6427191B1High performance fully dual-ported, pipelined cache designINTEL CORP·Filed 1998·Granted Jul 30, 2002·15 cites·23 claims
- 4640US6453427B2Method and apparatus for handling data errors in a computer systemINTEL CORP·Filed 1998·Granted Sep 17, 2002·13 cites·20 claims
- 4740US2003163643A1Bank conflict determinationFiled 2002·Application pending·0 cites
- 4839US6408380B1Execution of an instruction to load two independently selected registers in a single cycleINST THE DEV OF EMERGING ARCHI·Filed 1999·Granted Jun 18, 2002·10 cites·30 claims
- 4938US8769295B2Computing system feature activation mechanismMULLA DEAN·Filed 2005·Granted Jul 1, 2014·0 cites·19 claims
- 5038US6134636AMethod and apparatus for storing data in a memory arrayINTEL CORP·Filed 1998·Granted Oct 17, 2000·9 cites·20 claims
Showing the top 50 of 52 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →