Inventor · disambiguated record
Michael Fee
Also filed as: FEE MICHAEL · FEE MICHAEL F · FEE MICHAEL FRANCIS
93 granted patents·4 pending applications·282 citations·filing 1998–2022
99Inventor score
Files withIBM62AMBROLADZE EKATERINA M7BERGER DEANNA POSTLES DUNN6DUNN BERGER DEANNA POSTLES5BERGER DEANNA P4
Top patents by PatentIndex Score
97 records- 0194US9104581B2eDRAM refresh in a high performance cache architectureFEE MICHAEL·Filed 2010·Granted Aug 11, 2015·29 cites·11 claims
- 0293US11010210B2Controller address contention assumptionIBM·Filed 2019·Granted May 18, 2021·8 cites·20 claims
- 0391US11461151B2Controller address contention assumptionIBM·Filed 2021·Granted Oct 4, 2022·2 cites·20 claims
- 0489US8032716B2System, method and computer program product for providing a new quiesce stateIBM·Filed 2008·Granted Oct 4, 2011·20 cites·15 claims
- 0588US9477613B2Position-based replacement policy for address synonym management in shared cachesIBM·Filed 2015·Granted Oct 25, 2016·9 cites·18 claims
- 0688US9104583B2On demand allocation of cache buffer slotsAMBROLADZE EKATERINA M·Filed 2010·Granted Aug 11, 2015·13 cites·20 claims
- 0787US9507660B2Eliminate corrupted portions of cache during runtimeIBM·Filed 2016·Granted Nov 29, 2016·4 cites·1 claims
- 0885US9898407B2Configuration based cache coherency protocol selectionIBM·Filed 2015·Granted Feb 20, 2018·3 cites·11 claims
- 0985US6516393B1Dynamic serialization of memory access in a multi-processor systemIBM·Filed 2000·Granted Feb 4, 2003·43 cites·4 claims
- 1084US8244972B2Optimizing EDRAM refresh rates in a high performance cache architectureBRONSON TIMOTHY C·Filed 2010·Granted Aug 14, 2012·7 cites·17 claims
- 1183US9703661B2Eliminate corrupted portions of cache during runtimeIBM·Filed 2015·Granted Jul 11, 2017·3 cites·14 claims
- 1282US9923579B2Clock path technique for using on-chip circuitry to generate a correct encode pattern to test the on-chip circuitryIBM·Filed 2016·Granted Mar 20, 2018·2 cites·13 claims
- 1380US9858190B2Maintaining order with parallel access data streamsIBM·Filed 2015·Granted Jan 2, 2018·3 cites·12 claims
- 1480US9594689B2Designated cache data backup during system operationIBM·Filed 2015·Granted Mar 14, 2017·3 cites·17 claims
- 1579US10025608B2Quiesce handling in multithreaded environmentsIBM·Filed 2014·Granted Jul 17, 2018·4 cites·8 claims
- 1679US9734110B2Dynamic synchronous to asynchronous frequency transitions in high-performance symmetric multiprocessingIBM·Filed 2015·Granted Aug 15, 2017·3 cites·15 claims
- 1779US8996819B2Performance optimization and dynamic resource reservation for guaranteed coherency updates in a multi-level cache hierarchyIBM·Filed 2012·Granted Mar 31, 2015·4 cites·7 claims
- 1878US8352687B2Performance optimization and dynamic resource reservation for guaranteed coherency updates in a multi-level cache hierarchyIBM·Filed 2010·Granted Jan 8, 2013·4 cites·7 claims
- 1978US7739538B2Double data rate chaining for synchronous DDR interfacesIBM·Filed 2006·Granted Jun 15, 2010·9 cites·2 claims
- 2076US9104513B1Managing quiesce requests in a multi-processor environmentIBM·Filed 2014·Granted Aug 11, 2015·4 cites·6 claims
- 2175US9348524B1Memory controlled operations under dynamic relocation of storageIBM·Filed 2014·Granted May 24, 2016·3 cites·20 claims
- 2274US8566532B2Management of multipurpose command queues in a multilevel cache hierarchyDUNN BERGER DEANNA POSTLES·Filed 2010·Granted Oct 22, 2013·4 cites·18 claims
- 2374US8495287B2Clock-based debugging for embedded dynamic random access memory element in a processor coreCOLLURA ADAM B·Filed 2010·Granted Jul 23, 2013·4 cites·14 claims
- 2471US9678848B2Eliminate corrupted portions of cache during runtimeIBM·Filed 2016·Granted Jun 13, 2017·1 cites·1 claims
- 2571US9645904B2Dynamic cache row fail accumulation due to catastrophic failureIBM·Filed 2016·Granted May 9, 2017·1 cites·1 claims
- 2671US8327078B2Dynamic trailing edge latency absorption for fetch data forwarded from a shared data/control interfaceBERGER DEANNA POSTLES DUNN·Filed 2010·Granted Dec 4, 2012·3 cites·15 claims
- 2771US8250243B2Diagnostic data collection and storage put-away station in a multiprocessor systemBERGER DEANNA POSTLES DUNN·Filed 2010·Granted Aug 21, 2012·3 cites·27 claims
- 2870US9189415B2EDRAM refresh in a high performance cache architectureIBM·Filed 2012·Granted Nov 17, 2015·2 cites·11 claims
- 2970US9047199B2Reducing penalties for cache accessing operationsIBM·Filed 2013·Granted Jun 2, 2015·2 cites·16 claims
- 3069US8560767B2Optimizing EDRAM refresh rates in a high performance cache architectureBRONSON TIMOTHY C·Filed 2012·Granted Oct 15, 2013·2 cites·8 claims
- 3167US8499144B2Updating settings of a processor core concurrently to the operation of a multi core processor systemCONKLIN CHRISTOPHER R·Filed 2010·Granted Jul 30, 2013·4 cites·19 claims
- 3267US8447930B2Managing in-line store throughput reductionBERGER DEANNA P·Filed 2010·Granted May 21, 2013·2 cites·17 claims
- 3367US7574548B2Dynamic data transfer control method and apparatus for shared SMP computer systemsIBM·Filed 2007·Granted Aug 11, 2009·4 cites·20 claims
- 3466US9600361B2Dynamic partial blocking of a cache ECC bypassIBM·Filed 2015·Granted Mar 21, 2017·1 cites·6 claims
- 3566US8407420B2System, apparatus and method utilizing early access to shared cache pipeline for latency reductionDUNN BERGER DEANNA POSTLES·Filed 2010·Granted Mar 26, 2013·2 cites·19 claims
- 3665US10824565B2Configuration based cache coherency protocol selectionIBM·Filed 2019·Granted Nov 3, 2020·0 cites·20 claims
- 3765US8645796B2Dynamic pipeline cache error correctionAMBROLADZE EKATERINA M·Filed 2010·Granted Feb 4, 2014·2 cites·20 claims
- 3865US7779189B2Method, system, and computer program product for pipeline arbitrationIBM·Filed 2008·Granted Aug 17, 2010·3 cites·18 claims
- 3962US10402328B2Configuration based cache coherency protocol selectionIBM·Filed 2018·Granted Sep 3, 2019·0 cites·20 claims
- 4062US10394712B2Configuration based cache coherency protocol selectionIBM·Filed 2018·Granted Aug 27, 2019·0 cites·20 claims
- 4162US8521960B2Mitigating busy time in a high performance cacheBERGER DEANNA P·Filed 2010·Granted Aug 27, 2013·1 cites·16 claims
- 4261US8447932B2Recover store data mergingBERGER DEANNA P·Filed 2010·Granted May 21, 2013·1 cites·20 claims
- 4361US7752475B2Late data launch for a double data rate elastic interfaceIBM·Filed 2006·Granted Jul 6, 2010·2 cites·1 claims
- 4460US9929749B2Clock path technique for using on-chip circuitry to generate a correct encode pattern to test the on-chip circuitryIBM·Filed 2017·Granted Mar 27, 2018·0 cites·7 claims
- 4560US9915701B2Bypassing an encoded latch on a chip during a test-pattern scanIBM·Filed 2017·Granted Mar 13, 2018·0 cites·7 claims
- 4660US9886382B2Configuration based cache coherency protocol selectionIBM·Filed 2014·Granted Feb 6, 2018·0 cites·20 claims
- 4759US9665424B2Recovery improvement for quiesced systemsIBM·Filed 2014·Granted May 30, 2017·0 cites·7 claims
- 4859US8468536B2Multiple level linked LRU priorityBERGER DEANNA POSTLES DUNN·Filed 2010·Granted Jun 18, 2013·1 cites·15 claims
- 4958US10169260B2Multiprocessor cache buffer managementIBM·Filed 2017·Granted Jan 1, 2019·0 cites·20 claims
- 5058US9678830B2Recovery improvement for quiesced systemsIBM·Filed 2014·Granted Jun 13, 2017·0 cites·14 claims
Showing the top 50 of 97 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →