Inventor · disambiguated record
Arthur Joseph Hoane
Also filed as: HOANE ARTHUR J · HOANE ARTHUR JOSEPH · HOANE JR ARTHUR JOSEPH
16 granted patents·1 pending application·167 citations·filing 1991–2016
93Inventor score
Technology areasG06F
Top patents by PatentIndex Score
17 records- 0196US10339095B2Vector processor configured to operate on variable length vectors using digital signal processing instructionsOPTIMUM SEMICONDUCTOR TECH INC·Filed 2015·Granted Jul 2, 2019·18 cites·22 claims
- 0292US9959246B2Vector processor configured to operate on variable length vectors using implicitly typed instructionsOPTIMUM SEMICONDUCTOR TECH INC·Filed 2015·Granted May 1, 2018·6 cites·32 claims
- 0389US9910824B2Vector processor configured to operate on variable length vectors using instructions to combine and split vectorsOPTIMUM SEMICONDUCTOR TECH INC·Filed 2015·Granted Mar 6, 2018·4 cites·22 claims
- 0483US10908909B2Processor with mode supportOPTIMUM SEMICONDUCTOR TECH INC·Filed 2016·Granted Feb 2, 2021·4 cites·21 claims
- 0583US10824586B2Vector processor configured to operate on variable length vectors using one or more complex arithmetic instructionsOPTIMUM SEMICONDUCTOR TECH INC·Filed 2015·Granted Nov 3, 2020·2 cites·42 claims
- 0683US6990557B2Method and apparatus for multithreaded cache with cache eviction based on thread identifierSANDBRIDGE TECHNOLOGIES INC·Filed 2002·Granted Jan 24, 2006·38 cites·15 claims
- 0782US11544214B2Monolithic vector processor configured to operate on variable length vectors using a vector length registerOPTIMUM SEMICONDUCTOR TECH INC·Filed 2015·Granted Jan 3, 2023·2 cites·38 claims
- 0874US6912623B2Method and apparatus for multithreaded cache with simplified implementation of cache replacement policySANDBRIDGE TECHNOLOGIES INC·Filed 2002·Granted Jun 28, 2005·20 cites·15 claims
- 0973US10339094B2Vector processor configured to operate on variable length vectors with asymmetric multi-threadingOPTIMUM SEMICONDUCTOR TECH INC·Filed 2015·Granted Jul 2, 2019·1 cites·23 claims
- 1073US9558000B2Multithreading using an ordered list of hardware contextsOPTIMUM SEMICONDUCTOR TECH INC·Filed 2014·Granted Jan 31, 2017·3 cites·24 claims
- 1173US5715391AModular and infinitely extendable three dimensional torus packaging scheme for parallel processingIBM·Filed 1991·Granted Feb 3, 1998·66 cites·22 claims
- 1272US9766894B2Method and apparatus for enabling a processor to generate pipeline control signalsOPTIMUM SEMICONDUCTOR TECH INC·Filed 2014·Granted Sep 19, 2017·3 cites·26 claims
- 1360US10846259B2Vector processor to operate on variable length vectors with out-of-order executionOPTIMUM SEMICONDUCTOR TECH INC·Filed 2015·Granted Nov 24, 2020·0 cites·63 claims
- 1460US10733140B2Vector processor configured to operate on variable length vectors using instructions that change element widthsOPTIMUM SEMICONDUCTOR TECH INC·Filed 2015·Granted Aug 4, 2020·0 cites·58 claims
- 1559US10922267B2Vector processor to operate on variable length vectors using graphics processing instructionsOPTIMUM SEMICONDUCTOR TECH INC·Filed 2015·Granted Feb 16, 2021·0 cites·14 claims
- 1659US2016224514A1Vector processor configured to operate on variable length vectors with register renamingOPTIMUM SEMICONDUCTOR TECH INC·Filed 2015·Application pending·0 cites
- 1741US8762641B2Method for achieving power savings by disabling a valid arrayHOANE JR ARTHUR JOSEPH·Filed 2009·Granted Jun 24, 2014·0 cites·19 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →