Inventor · disambiguated record
Deshanand Singh
Also filed as: SINGH DESHANAND · SINGH DESHANAND P · SINGH DESHANAND PRATAP
56 granted patents·6 pending applications·653 citations·filing 2002–2023
99Inventor score
Top patents by PatentIndex Score
62 records- 0194US8296695B1Method and apparatus for performing fast incremental resynthesisCHEN DORIS TZU LANG·Filed 2010·Granted Oct 23, 2012·25 cites·35 claims
- 0294US7500216B1Method and apparatus for performing physical synthesis hill-climbing on multi-processor machinesALTERA CORP·Filed 2007·Granted Mar 3, 2009·42 cites·27 claims
- 0393US9100012B1Adaptable programs using partial reconfigurationALTERA CORP·Filed 2012·Granted Aug 4, 2015·13 cites·20 claims
- 0493US8918748B1M/A for performing automatic latency optimization on system designs for implementation on programmable hardwareCHIU GORDON RAYMOND·Filed 2012·Granted Dec 23, 2014·21 cites·20 claims
- 0593US8499201B1Methods and systems for measuring and presenting performance data of a memory controller systemCHIU GORDON RAYMOND·Filed 2010·Granted Jul 30, 2013·25 cites·25 claims
- 0692US9690278B1Method and apparatus for high-level programs with general control flowALTERA CORP·Filed 2014·Granted Jun 27, 2017·15 cites·20 claims
- 0792US9515658B1Method and apparatus for implementing configurable streaming networksALTERA CORP·Filed 2014·Granted Dec 6, 2016·8 cites·21 claims
- 0892US8959469B2Configuring a programmable device using high-level languageCHEN DORIS TZU-LANG·Filed 2012·Granted Feb 17, 2015·16 cites·24 claims
- 0991US7107477B1Programmable logic devices with skewed clocking signalsALTERA CORP·Filed 2003·Granted Sep 12, 2006·45 cites·36 claims
- 1090US8296696B1Method and apparatus for performing simultaneous register retiming and combinational resynthesis during physical synthesisCHIU GORDON RAYMOND·Filed 2008·Granted Oct 23, 2012·24 cites·21 claims
- 1189US9548740B1Multiple alternate configurations for an integrated circuit deviceALTERA CORP·Filed 2013·Granted Jan 17, 2017·12 cites·26 claims
- 1287US11171652B2Method and apparatus for implementing configurable streaming networksALTERA CORP·Filed 2020·Granted Nov 9, 2021·2 cites·20 claims
- 1387US10599404B1M/A for compiling parallel program having barrier synchronization for programmable hardwareNETO DAVID·Filed 2012·Granted Mar 24, 2020·17 cites·27 claims
- 1487US8732634B1Method and apparatus for performing fast incremental resynthesisALTERA CORP·Filed 2013·Granted May 20, 2014·7 cites·23 claims
- 1586US9449132B2Configuring a programmable device using high-level languageALTERA CORP·Filed 2015·Granted Sep 20, 2016·4 cites·24 claims
- 1686US8806403B1Efficient configuration of an integrated circuit device using high-level languageALTERA CORP·Filed 2013·Granted Aug 12, 2014·9 cites·20 claims
- 1786US8214701B1Hardware and software debuggingMALHOTRA SHAWN·Filed 2009·Granted Jul 3, 2012·19 cites·20 claims
- 1885US7996797B1Method and apparatus for performing multiple stage physical synthesisALTERA CORP·Filed 2007·Granted Aug 9, 2011·10 cites·32 claims
- 1985US7464286B1Programmable logic devices with skewed clocking signalsALTERA CORP·Filed 2006·Granted Dec 9, 2008·12 cites·25 claims
- 2085US7254801B1Synthesis aware placement: a novel approach that combines knowledge of possible resynthesisALTERA CORP·Filed 2005·Granted Aug 7, 2007·15 cites·40 claims
- 2184US11205152B1Virtual logistical network overlay for physical logistical networkAMAZON TECH INC·Filed 2016·Granted Dec 21, 2021·3 cites·20 claims
- 2284US8856702B1Method and apparatus for performing multiple stage physical synthesisALTERA CORP·Filed 2013·Granted Oct 7, 2014·5 cites·21 claims
- 2384US8510688B1Method and apparatus for performing multiple stage physical synthesisSINGH DESHANAND·Filed 2011·Granted Aug 13, 2013·6 cites·19 claims
- 2484US8484596B1Method and apparatus for performing fast incremental resynthesisCHEN DORIS TZU LANG·Filed 2012·Granted Jul 9, 2013·6 cites·23 claims
- 2584US8095914B1Methods for instruction trace decompositionSINGH DESHANAND·Filed 2007·Granted Jan 10, 2012·15 cites·16 claims
- 2683US9922150B1Method and apparatus for satisfying operating conditions in a system design using an electronic design automation toolALTERA CORP·Filed 2014·Granted Mar 20, 2018·8 cites·21 claims
- 2783US8589849B1Method and apparatus for implementing soft constraints in tools used for designing programmable logic devicesBORER TERRY·Filed 2007·Granted Nov 19, 2013·10 cites·30 claims
- 2883US6779169B1Method and apparatus for placement of components onto programmable logic devicesALTERA CORP·Filed 2002·Granted Aug 17, 2004·32 cites·24 claims
- 2982US10615800B1Method and apparatus for implementing configurable streaming networksALTERA CORP·Filed 2019·Granted Apr 7, 2020·2 cites·20 claims
- 3080US10366189B2Configuring a programmable device using high-level languageALTERA CORP·Filed 2016·Granted Jul 30, 2019·2 cites·19 claims
- 3180US7318210B1Method and apparatus for performing incremental placement for layout-driven optimizations on field programmable gate arraysALTERA CORP·Filed 2006·Granted Jan 8, 2008·8 cites·26 claims
- 3279US7360190B1Method and apparatus for performing retiming on field programmable gate arraysALTERA CORP·Filed 2004·Granted Apr 15, 2008·25 cites·31 claims
- 3379US7257800B1Method and apparatus for performing logic replication in field programmable gate arraysALTERA CORP·Filed 2004·Granted Aug 14, 2007·28 cites·34 claims
- 3479US7191426B1Method and apparatus for performing incremental compilation on field programmable gate arraysALTERA CORP·Filed 2004·Granted Mar 13, 2007·27 cites·32 claims
- 3578US8032855B1Method and apparatus for performing incremental placement on a structured application specific integrated circuitALTERA CORP·Filed 2005·Granted Oct 4, 2011·9 cites·28 claims
- 3676US10033387B2Method apparatus for high-level programs with general control flowALTERA CORP·Filed 2017·Granted Jul 24, 2018·2 cites·20 claims
- 3776US9703696B1Guided memory buffer allocationALTERA CORP·Filed 2013·Granted Jul 11, 2017·5 cites·18 claims
- 3876US7620925B1Method and apparatus for performing post-placement routability optimizationALTERA CORP·Filed 2006·Granted Nov 17, 2009·7 cites·16 claims
- 3975US9147023B1Method and apparatus for performing fast incremental resynthesisALTERA CORP·Filed 2014·Granted Sep 29, 2015·2 cites·22 claims
- 4074US7290240B1Leveraging combinations of synthesis, placement and incremental optimizationsALTERA CORP·Filed 2004·Granted Oct 30, 2007·25 cites·37 claims
- 4174US7290239B1Method and apparatus for performing post-placement functional decomposition for field programmable gate arraysALTERA CORP·Filed 2004·Granted Oct 30, 2007·18 cites·14 claims
- 4274US7194720B1Method and apparatus for implementing soft constraints in tools used for designing systems on programmable logic devicesALTERA CORP·Filed 2003·Granted Mar 20, 2007·19 cites·26 claims
- 4371US7509597B1Method and apparatus for performing post-placement functional decomposition on field programmable gate arrays using binary decision diagramsALTERA CORP·Filed 2005·Granted Mar 24, 2009·5 cites·19 claims
- 4471US7444613B1Systems and methods for mapping arbitrary logic functions into synchronous embedded memoriesALTERA CORP·Filed 2006·Granted Oct 28, 2008·4 cites·38 claims
- 4571US7412677B1Detecting reducible registersALTERA CORP·Filed 2006·Granted Aug 12, 2008·5 cites·30 claims
- 4667US9754065B2Method and apparatus for implementing soft constraints in tools used for designing programmable logic devicesALTERA CORP·Filed 2013·Granted Sep 5, 2017·1 cites·20 claims
- 4767US7181717B1Method and apparatus for placement of components onto programmable logic devicesALTERA CORP·Filed 2004·Granted Feb 20, 2007·10 cites·16 claims
- 4864US7797666B1Systems and methods for mapping arbitrary logic functions into synchronous embedded memoriesALTERA CORP·Filed 2008·Granted Sep 14, 2010·2 cites·20 claims
- 4963US7594204B1Method and apparatus for performing layout-driven optimizations on field programmable gate arraysALTERA CORP·Filed 2003·Granted Sep 22, 2009·8 cites·17 claims
- 5062US7197734B1Method and apparatus for designing systems using logic regionsALTERA CORP·Filed 2002·Granted Mar 27, 2007·12 cites·30 claims
Showing the top 50 of 62 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →