Inventor · disambiguated record
George V. Rouse
Also filed as: ROUSE GEORGE V
25 granted patents·1 pending application·1,616 citations·filing 1987–2004
98Inventor score
Top patents by PatentIndex Score
26 records- 0196US5569620ABonded wafer processing with metal silicidationHARRIS CORP·Filed 1994·Granted Oct 29, 1996·194 cites·13 claims
- 0294US5849627ABonded wafer processing with oxidative bondingHARRIS CORP·Filed 1995·Granted Dec 15, 1998·178 cites·5 claims
- 0394US5387555ABonded wafer processing with metal silicidationHARRIS CORP·Filed 1992·Granted Feb 7, 1995·149 cites·8 claims
- 0493US5034343AManufacturing ultra-thin wafer using a handle waferHARRIS CORP·Filed 1990·Granted Jul 23, 1991·171 cites·16 claims
- 0589US5362667ABonded wafer processingHARRIS CORP·Filed 1992·Granted Nov 8, 1994·93 cites·26 claims
- 0688US6246090B1Power trench transistor device source region formation using silicon spacerINTERSIL CORP·Filed 2000·Granted Jun 12, 2001·43 cites·13 claims
- 0786US5744852ABonded waferHARRIS CORP·Filed 1996·Granted Apr 28, 1998·68 cites·8 claims
- 0886US5240876AMethod of fabricating SOI wafer with SiGe as an etchback film in a BESOI processHARRIS CORP·Filed 1992·Granted Aug 31, 1993·90 cites·8 claims
- 0986US5218213ASOI wafer with sigeHARRIS CORP·Filed 1992·Granted Jun 8, 1993·83 cites·10 claims
- 1084US6255195B1Method for forming a bonded substrate containing a planar intrinsic gettering zone and substrate formed by said methodINTERSIL CORP·Filed 1999·Granted Jul 3, 2001·66 cites·23 claims
- 1183US5091331AUltra-thin circuit fabrication by controlled wafer debondingHARRIS CORP·Filed 1990·Granted Feb 25, 1992·84 cites·16 claims
- 1280US5517047ABonded wafer processingHARRIS CORP·Filed 1994·Granted May 14, 1996·53 cites·5 claims
- 1378US4851078ADielectric isolation process using double wafer bondingHARRIS CORP·Filed 1987·Granted Jul 25, 1989·52 cites·21 claims
- 1476US6798024B1BiCMOS process with low temperature coefficient resistor (TCRL)INTERSIL INC·Filed 2000·Granted Sep 28, 2004·25 cites·18 claims
- 1574US6455379B2Power trench transistor device source region formation using silicon spacerFAIRCHILD SEMICONDUCTOR·Filed 2001·Granted Sep 24, 2002·18 cites·12 claims
- 1674US5932022ASC-2 based pre-thermal treatment wafer cleaning processHARRIS CORP·Filed 1998·Granted Aug 3, 1999·51 cites·3 claims
- 1772US5603779ABonded wafer and method of fabrication thereofHARRIS CORP·Filed 1995·Granted Feb 18, 1997·35 cites·28 claims
- 1867US6825532B2Bonded substrate for an integrated circuit containing a planar intrinsic gettering zoneINTERSIL INC·Filed 2001·Granted Nov 30, 2004·12 cites·32 claims
- 1965US5081061AManufacturing ultra-thin dielectrically isolated wafersHARRIS CORP·Filed 1991·Granted Jan 14, 1992·38 cites·4 claims
- 2064US5266135AWafer bonding process employing liquid oxidantHARRIS CORP·Filed 1992·Granted Nov 30, 1993·29 cites·29 claims
- 2163US4968628AMethod of fabricating back diffused bonded oxide substratesHARRIS CORP·Filed 1988·Granted Nov 6, 1990·28 cites·19 claims
- 2262US6909146B1Bonded wafer with metal silicidationINTERSIL CORP·Filed 1999·Granted Jun 21, 2005·25 cites·6 claims
- 2360US6812108B2BICMOS process with low temperature coefficient resistor (TCRL)INTERSIL CORP·Filed 2003·Granted Nov 2, 2004·9 cites·41 claims
- 2455US7052973B2Bonded substrate for an integrated circuit containing a planar intrinsic gettering zoneINTERSIL INC·Filed 2004·Granted May 30, 2006·5 cites·18 claims
- 2551US5334273AWafer bonding using trapped oxidizing vaporHARRIS CORP·Filed 1993·Granted Aug 2, 1994·17 cites·23 claims
- 2622US2002189640A1Sc-2 based pre-thermal treatment wafer cleaning processFiled 1999·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →